MC9328MXS Datasheet, PDF (70/74 Pages) List of Unclassifed Manufacturers – Advance Information

Functional Description and Application Information
Table 30. SSI (Port B Alternate Function) Timing Parameter Table (Continued)
Ref
No.
Parameter
1.8 ± 0.1 V
3.0 ± 0.3 V
Unit
Minimum Maximum Minimum Maximum
External Clock Operation (Port B Alternate Function²)
15 STCK/SRCK clock period¹
92.8
–
81.4
16 STCK/SRCK clock high period
27.1
–
40.7
17 STCK/SRCK clock low period
18 STCK high to STFS (bl) high³
19 SRCK high to SRFS (bl) high³
20 STCK high to STFS (bl) low³
21 SRCK high to SRFS (bl) low³
22 STCK high to STFS (wl) high³
23 SRCK high to SRFS (wl) high³
24 STCK high to STFS (wl) low³
25 SRCK high to SRFS (wl) low³
61.1
–
40.7
–
92.8
0
–
92.8
0
–
92.8
0
–
92.8
0
–
92.8
0
–
92.8
0
–
92.8
0
–
92.8
0
26 STCK high to STXD valid from high impedance
18.9
29.07
16.6
27a STCK high to STXD high
9.23
20.75
8.1
27b STCK high to STXD low
10.60
21.32
9.3
28 STCK high to STXD high impedance
17.90
29.75
15.7
29 SRXD setup time before SRCK low
1.14
–
1.0
30 SRXD hold time after SRCK low
0
–
0
–
ns
–
ns
–
ns
81.4
ns
81.4
ns
81.4
ns
81.4
ns
81.4
ns
81.4
ns
81.4
ns
81.4
ns
25.5
ns
18.2
ns
18.7
ns
26.1
ns
–
ns
–
ns
Synchronous Internal Clock Operation (Port B Alternate Function²)
31 SRXD setup before STCK falling
32 SRXD hold after STCK falling
18.81
–
16.5
–
ns
0
–
0
–
ns
Synchronous External Clock Operation (Port B Alternate Function²)
33 SRXD setup before STCK falling
1.14
–
1.0
–
ns
34 SRXD hold after STCK falling
0
–
0
–
ns
1 _{All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync}
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting
the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.
2 _{There are 2 set of I/O signals for the SSI module. They are from Port C primary function (pad 257 to pad 261) and Port B}
alternate function (pad 283 to pad 288). When SSI signals are configured as outputs, they can be viewed both at Port C primary
function and Port B alternate function. When SSI signals are configured as inputs, the SSI module selects the input based on
FMCR register bits in the Clock controller module (CRM). By default, the input are selected from Port C primary function.
3 _{bl = bit length; wl = word length.}
MC9328MXS Technical Data, Rev. 3
70
Freescale Semiconductor