MC9328MXS Datasheet, PDF (6/74 Pages) List of Unclassifed Manufacturers – Advance Information

Signals and Connections
Table 2. i.MXS Signal Descriptions (Continued)
Signal Name
Function/Notes
ETM
ETMTRACESYNC ETM sync signal which is multiplexed with A24. ETMTRACESYNC is selected in ETM mode.
ETMTRACECLK
ETM clock signal which is multiplexed with A23. ETMTRACECLK is selected in ETM mode.
ETMPIPESTAT [2:0] ETM status signals which are multiplexed with A [22:20]. ETMPIPESTAT [2:0] are selected in ETM
mode.
ETMTRACEPKT [7:0] ETM packet signals which are multiplexed with ECB, LBA, BCLK (burst clock), PA17, A [19:16].
ETMTRACEPKT [7:0] are selected in ETM mode.
LCD Controller
LD [15:0]
FLM/VSYNC
LP/HSYNC
LSCLK
ACD/OE
CONTRAST
SPL_SPR
PS
CLS
REV
LCD Data Bus—All LCD signals are driven low after reset and when LCD is off.
Frame Sync or Vsync—This signal also serves as the clock signal output for the gate
driver (dedicated signal SPS for Sharp panel HR-TFT).
Line pulse or H sync
Shift clock
Alternate crystal direction/output enable.
This signal is used to control the LCD bias voltage as contrast control.
Program horizontal scan direction (Sharp panel dedicated signal).
Control signal output for source driver (Sharp panel dedicated signal).
Start signal output for gate driver. This signal is an inverted version of PS (Sharp panel dedicated
signal).
Signal for common electrode driving signal preparation (Sharp panel dedicated signal).
SPI 1
SPI1_MOSI
SPI1_MISO
SPI1_SS
SPI1_SCLK
SPI1_SPI_RDY
Master Out/Slave In
Slave In/Master Out
Slave Select (Selectable polarity)
Serial Clock
Serial Data Ready
General Purpose Timers
TIN
TMR2OUT
Timer Input Capture or Timer Input Clock—The signal on this input is applied to both timers
simultaneously.
Timer 2 Output
USB Device
USBD_VMO
USBD_VPO
USBD_VM
USBD_VP
USB Minus Output
USB Plus Output
USB Minus Input
USB Plus Input
MC9328MXS Technical Data, Rev. 3
6
Freescale Semiconductor