MC9328MXS Datasheet, PDF (20/74 Pages) List of Unclassifed Manufacturers – Advance Information

Functional Description and Application Information
4.2 DPLL Timing Specifications
Parameters of the DPLL are given in Table 10. In this table, T_ref is a reference clock period after the
pre-divider and T_dck is the output double clock period.
Table 10. DPLL Specifications
Parameter
Test Conditions
Minimum Typical Maximum Unit
DPLL input clock freq range Vcc = 1.8V
5
–
100
MHz
Pre-divider output clock
freq range
Vcc = 1.8V
5
–
30
MHz
DPLL output clock freq range Vcc = 1.8V
80
–
220
MHz
Pre-divider factor (PD)
–
1
–
16
–
Total multiplication factor (MF) Includes both integer and fractional parts
5
–
15
–
MF integer part
–
5
–
15
–
MF numerator
Should be less than the denominator
0
–
1022
–
MF denominator
–
1
–
1023
–
Pre-multiplier lock-in time
–
–
–
312.5
μsec
Freq lock-in time after
full reset
FOL mode for non-integer MF
(does not include pre-multi lock-in time)
250
280
(56 μs)
300
T_ref
Freq lock-in time after
partial reset
FOL mode for non-integer MF (does not
include pre-multi lock-in time)
220
250
(50 μs)
270
T_ref
Phase lock-in time after
full reset
FPL mode and integer MF (does not include
pre-multi lock-in time)
300
350
(70 μs)
400
T_ref
Phase lock-in time after
partial reset
FPL mode and integer MF (does not include
pre-multi lock-in time)
270
320
(64 μs)
370
T_ref
Freq jitter (p-p)
–
–
0.005
(0.01%)
0.01
2•T_dck
Phase jitter (p-p)
Integer MF, FPL mode, Vcc=1.8V
–
1.0
(10%)
1.5
ns
Power supply voltage
–
1.7
–
2.5
V
Power dissipation
FOL mode, integer MF,
f_dck = 100 MHz, Vcc = 1.8V
–
–
4
mW
4.3 Reset Module
The timing relationships of the Reset module with the POR and RESET_IN are shown in Figure 3 and
Figure 4.
NOTE
Be aware that NVDD must ramp up to at least 1.8V before QVDD is powered up
to prevent forward biasing.
MC9328MXS Technical Data, Rev. 3
20
Freescale Semiconductor