MC9328MXS Datasheet, PDF (16/74 Pages) List of Unclassifed Manufacturers – Advance Information

Electrical Characteristics
3 Electrical Characteristics
This section contains the electrical specifications and timing diagrams for the i.MXS processor.
3.1 Maximum Ratings
Table 4 provides information on maximum ratings which are those values beyond which damage to the
device may occur. Functional operation should be restricted to the limits listed in Recommended Operating
Range Table 5 on page 17 or the DC Characteristics table.
Table 4. Maximum Ratings
Symbol
Rating
Minimum
Maximum
Unit
NV_DD
DC I/O Supply Voltage
-0.3
3.3
V
QV_DD
DC Internal (core = 100 MHz) Supply Voltage
-0.3
1.9
V
AV_DD
DC Analog Supply Voltage
-0.3
3.3
V
BTRFV_DD
DC Bluetooth Supply Voltage
-0.3
3.3
V
VESD_HBM ESD immunity with HBM (human body model)
–
2000
V
VESD_MM ESD immunity with MM (machine model)
–
100
V
ILatchup
Latch-up immunity
–
200
mA
Test
Storage temperature
-55
150
°C
Pmax
Power Consumption
800¹
1300²
mW
1 _{A typical application with 30 pads simultaneously switching assumes the GPIO toggling and instruction fetches from the ARM}®
core-that is, 7x GPIO, 15x Data bus, and 8x Address bus.
2 _{A worst-case application with 70 pads simultaneously switching assumes the GPIO toggling and instruction fetches from the}
ARM core-that is, 32x GPIO, 30x Data bus, 8x Address bus. These calculations are based on the core running its heaviest OS
application at 100MHz, and where the whole image is running out of SDRAM. QVDD at 1.9V, NVDD and AVDD at 3.3V,
therefore, 180mA is the worst measurement recorded in the factory environment, max 5mA is consumed for OSC pads, with
each toggle GPIO consuming 4mA.
3.2 Recommended Operating Range
Table 5 provides the recommended operating ranges for the supply voltages and temperatures. The i.MXS
processor has multiple pairs of VDD and VSS power supply and return pins. QVDD and QVSS pins are
used for internal logic. All other VDD and VSS pins are for the I/O pads voltage supply, and each pair of
VDD and VSS provides power to the enclosed I/O pads. This design allows different peripheral supply
voltage levels in a system.
Because AVDD pins are supply voltages to the analog pads, it is recommended to isolate and noise-filter
the AVDD pins from other VDD pins.
For more information about I/O pads grouping per VDD, please refer to Table 2 on page 4.
MC9328MXS Technical Data, Rev. 3
16
Freescale Semiconductor