MC9328MXS Datasheet, PDF (53/74 Pages) List of Unclassifed Manufacturers – Advance Information

4.4.4 Non-TFT Panel Timing
T1
VSYN
Functional Description and Application Information
T1
T2
T3
XMAX
T4
T2
HSYN
SCLK
Ts
LD[15:0]
Figure 33. Non-TFT Panel Timing
Table 17. Non TFT Panel Timing Diagram
Symbol
Parameter
Allowed Register
Minimum Value^{1, 2}
Actual Value
Unit
T1
HSYN to VSYN delay³
0
HWAIT2+2
Tpix⁴
T2 HSYN pulse width
0
HWIDTH+1
Tpix
T3 VSYN to SCLK
–
0 ≤ T3 ≤ Ts⁵
–
T4 SCLK to HSYN
0
HWAIT1+1
Tpix
1 _{Maximum frequency of LCDC_CLK is 48 MHz, which is controlled by Peripheral Clock Divider Register.}
2 _{Maximum frequency of SCLK is HCLK / 5, otherwise LD output will be wrong.}
3 _{VSYN, HSYN and SCLK can be programmed as active high or active low. In the above timing diagram, all}
these 3 signals are active high.
4 _{Tpix is the pixel clock period which equals LCDC_CLK period * (PCD + 1).}
5 _{Ts is the shift clock period. Ts = Tpix * (panel data bus width).}
4.5 SPI Timing Diagrams
To use the internal transmit (TX) and receive (RX) data FIFOs when the SPI module is configured as a
master, two control signals are used for data transfer rate control: the SS signal (output) and the SPI_RDY
signal (input). The SPI1 Sample Period Control Register (PERIODREG1) can also be programmed to a
fixed data transfer rate. When the SPI module is configured as a slave, the user can configure the SPI1
Control Register (CONTROLREG1) to match the external SPI master’s timing. In this configuration, SS
becomes an input signal, and is used to latch data into or load data out to the internal data shift registers,
as well as to increment the data FIFO. Figure 34 through Figure 38 show the timing relationship of the
master SPI using different triggering mechanisms.
MC9328MXS Technical Data, Rev. 3
Freescale Semiconductor
53