MC9328MXS Datasheet, PDF (19/74 Pages) List of Unclassifed Manufacturers – Advance Information

Functional Description and Application Information
4.1 Embedded Trace Macrocell
All registers in the ETM9 are programmed through a JTAG interface. The interface is an extension of the
ARM920T processor’s TAP controller, and is assigned scan chain 6. The scan chain consists of a 40-bit
shift register comprised of the following:
• 32-bit data field
• 7-bit address field
• A read/write bit
The data to be written is scanned into the 32-bit data field, the address of the register into the 7-bit address
field, and a 1 into the read/write bit.
A register is read by scanning its address into the address field and a 0 into the read/write bit. The 32-bit
data field is ignored. A read or a write takes place when the TAP controller enters the UPDATE-DR state.
The timing diagram for the ETM9 is shown in Figure 2. See Table 9 for the ETM9 timing parameters used
in Figure 2.
2a
1
3a
2b
TRACECLK
3b
TRACECLK
(Half-Rate Clocking Mode)
Output Trace Port
Valid Data
4a
Figure 2. Trace Port Timing Diagram
Valid Data
4b
Table 9. Trace Port Timing Diagram Parameter Table
Ref No.
Parameter
1 CLK frequency
2a Clock high time
2b Clock low time
3a Clock rise time
3b Clock fall time
4a Output hold time
4b Output setup time
1.8 ± 0.1 V
Minimum
0
1.3
3
–
–
2.28
3.42
Maximum
85
–
–
4
3
–
–
3.0 ± 0.3 V
Minimum
0
2
2
–
–
2
3
Maximum
100
–
–
3
3
–
–
Unit
MHz
ns
ns
ns
ns
ns
ns
MC9328MXS Technical Data, Rev. 3
Freescale Semiconductor
19