MC9328MXS Datasheet, PDF (62/74 Pages) List of Unclassifed Manufacturers – Advance Information

Functional Description and Application Information
Table 25. SDRAM Refresh Timing Parameter Table
Ref No.
Parameter
1.8 ± 0.1 V
3.0 ± 0.3 V
Unit
Minimum
Maximum
Minimum
Maximum
1 SDRAM clock high-level width
2.67
–
4
–
ns
2 SDRAM clock low-level width
6
–
4
–
ns
3 SDRAM clock cycle time
11.4
–
10
–
ns
4 Address setup time
3.42
–
3
–
ns
5 Address hold time
2.28
–
2
–
ns
6 Precharge cycle period
t_RP1
–
t_RP1
–
ns
7 Auto precharge command period
t_RC1
–
t_RC1
–
ns
1 _{tRP and tRC = SDRAM clock cycle time. These settings can be found in the MC9328MXS reference manual.}
SDCLK
CS
RAS
CAS
WE
ADDR
DQ
DQM
CKE
BA
Figure 46. SDRAM Self-Refresh Cycle Timing Diagram
MC9328MXS Technical Data, Rev. 3
62
Freescale Semiconductor