MC9S08QD4_07 Datasheet, PDF (43/202 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU)

START
FACCERR ?
1
CLEAR ERROR
Chapter 4 Memory Map and Register Definition
0
WRITE TO FCDIV⁽¹⁾
0
FCBEF ?
1
WRITE TO FLASH
TO BUFFER ADDRESS AND DATA
(1) _{Required only once}
after reset.
WRITE COMMAND TO FCMD
WRITE 1 TO FCBEF
TO LAUNCH COMMAND
AND CLEAR FCBEF ⁽²⁾
(2) _{Wait at least four bus cycles before}
checking FCBEF or FCCF.
FPVIO OR
YES
FACCERR ?
YES
NO
NEW BURST COMMAND ?
NO
ERROR EXIT
0
FCCF ?
1
DONE
Figure 4-3. Flash Burst Program Flowchart
4.5.5 Access Errors
An access error occurs whenever the command execution protocol is violated.
Any of the following specific actions will cause the access error flag (FACCERR) in FSTAT to be set.
FACCERR must be cleared by writing a 1 to FACCERR in FSTAT before any command can be
processed.
• Writing to a flash address before the internal flash clock frequency has been set by writing to the
FCDIV register
• Writing to a flash address while FCBEF is not set (A new command cannot be started until the
command buffer is empty.)
MC9S08QD4 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
43