MC9S08QD4_07 Datasheet, PDF (173/202 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU)

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7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
BDFR¹
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
1 _{BDFR is writable only through serial background mode debug commands, not from user programs.}
Figure 12-6. System Background Debug Force Reset Register (SBDFR)
Table 12-3. SBDFR Register Field Description
Field
0
BDFR
Description
Background Debug Force Reset — A serial active background mode command such as WRITE_BYTE allows
an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot
be written from a user program.
MC9S08QD4 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
173