MC9S08QD4_07 Datasheet, PDF (113/202 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU)

Analog-to-Digital Converter (S08ADC10V1)
result of the conversion is transferred to ADCRH and ADCRL upon completion of the conversion
algorithm.
If the bus frequency is less than the f_ADCK frequency, precise sample time for continuous conversions
cannot be guaranteed when short sample is enabled (ADLSMP=0). If the bus frequency is less than 1/11th
of the f_ADCK frequency, precise sample time for continuous conversions cannot be guaranteed when long
sample is enabled (ADLSMP=1).
The maximum total conversion time for different conditions is summarized in Table 8-12.
Table 8-12. Total Conversion Time vs. Control Conditions
Conversion Type
Single or first continuous 8-bit
Single or first continuous 10-bit
Single or first continuous 8-bit
Single or first continuous 10-bit
Single or first continuous 8-bit
Single or first continuous 10-bit
Single or first continuous 8-bit
Single or first continuous 10-bit
Subsequent continuous 8-bit;
f_BUS > f_ADCK
Subsequent continuous 10-bit;
f_BUS > f_ADCK
Subsequent continuous 8-bit;
f_BUS > f_ADCK/11
Subsequent continuous 10-bit;
f_BUS > f_ADCK/11
ADICLK
0x, 10
0x, 10
0x, 10
0x, 10
11
11
11
11
xx
xx
xx
xx
ADLSMP
0
0
1
1
0
0
1
1
0
0
1
1
Max Total Conversion Time
20 ADCK cycles + 5 bus clock cycles
23 ADCK cycles + 5 bus clock cycles
40 ADCK cycles + 5 bus clock cycles
43 ADCK cycles + 5 bus clock cycles
5 μs + 20 ADCK + 5 bus clock cycles
5 μs + 23 ADCK + 5 bus clock cycles
5 μs + 40 ADCK + 5 bus clock cycles
5 μs + 43 ADCK + 5 bus clock cycles
17 ADCK cycles
20 ADCK cycles
37 ADCK cycles
40 ADCK cycles
The maximum total conversion time is determined by the clock source chosen and the divide ratio selected.
The clock source is selectable by the ADICLK bits, and the divide ratio is specified by the ADIV bits. For
example, in 10-bit mode, with the bus clock selected as the input clock source, the input clock divide-by-1
ratio selected, and a bus frequency of 8 MHz, then the conversion time for a single conversion is:
23 ADCK cyc
5 bus cyc
Conversion time =
8 MHz/1
+ _{8 MHz}
= 3.5 μs
Number of bus cycles = 3.5 μs x 8 MHz = 28 cycles
NOTE
The ADCK frequency must be between f_ADCK minimum and f_ADCK
maximum to meet ADC specifications.
MC9S08QD4 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
113