MC9S08QD4_07 Datasheet, PDF (24/202 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU)

Chapter 2 External Signal Description
Although the BKGD pin is a pseudo open-drain pin, the background debug communication protocol
provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from
cables and the absolute value of the internal pullup device play almost no role in determining rise and fall
times on the BKGD pin.
2.2.5 General-Purpose I/O and Peripheral Ports
The MC9S08QD4 series of MCUs support up to 4 general-purpose I/O pins, 1 input-only pin and 1
output-only pin, which are shared with on-chip peripheral functions (timers, serial I/O, ADC, keyboard
interrupts, etc.). On each of the MC9S08QD4 series devices there is one input-only and one output-only
port pin.
When a port pin is configured as a general-purpose output or a peripheral uses the port pin as an output,
software can select one of two drive strengths and enable or disable slew rate control. When a port pin is
configured as a general-purpose input or a peripheral uses the port pin as an input, software can enable a
pullup device.
For information about controlling these pins as general-purpose I/O pins, see the Chapter 6, “Parallel
Input/Output Control.” For information about how and when on-chip peripheral systems use these pins,
see the appropriate chapter referenced in Table 2-1.
Immediately after reset, all pins that are not output-only are configured as high-impedance,
general-purpose inputs with internal pullup devices disabled. After reset, the output-only port function is
not enabled but is configured for low output drive strength with slew rate control enabled. The PTA4 pin
defaults to BKGD/MS on any reset.
NOTE
To avoid extra current drain from floating input pins, the reset initialization
routine in the application program must either enable on-chip pullup devices
or change the direction of unused pins to outputs so the pins do not float.
2.2.5.1 Pin Control Registers
To select drive strength or enable slew rate control or pullup devices, the user writes to the appropriate pin
control register located in the high-page register block of the memory map. The pin control registers
operate independently of the parallel I/O registers and allow control of a port on an individual pin basis.
2.2.5.1.1 Internal Pullup Enable
An internal pullup device can be enabled for each port pin by setting the corresponding bit in one of the
pullup enable registers (PTxPEn). The pullup device is disabled if the pin is configured as an output by the
parallel I/O control logic or any shared peripheral function, regardless of the state of the corresponding
pullup enable register bit. The pullup device is also disabled if the pin is controlled by an analog function.
The KBI module and IRQ function when enabled for rising edge detection causes an enabled internal pull
device to be configured as a pulldown.
MC9S08QD4 Series MCU Data Sheet, Rev. 3
24
Freescale Semiconductor