MC35XS3400 Datasheet, PDF (40/45 Pages) Freescale Semiconductor, Inc – Quad High Side Switch (Quad 35mΩ)

ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 1.0)
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 1.0)
35XS3400PNA
Introduction
This thermal addendum is provided as a supplement to the 35XS3400
technical data sheet. The addendum provides thermal performance
information that may be critical in the design and development of system
applications. All electrical, application and packaging information is
provided in the data sheet.
24-PIN
PQFN
Package and Thermal Considerations
This 35XS3400 is a dual die package. There are two heat sources in the
package independently heating with P₁ and P₂. This results in two junction
temperatures, T_J1 and T_J2, and a thermal resistance matrix with R_θJAmn.
For m, n = 1, R_θJA11 is the thermal resistance from Junction 1 to the
reference temperature while only heat source 1 is heating with P₁.
For m = 1, n = 2, R_θJA12 is the thermal resistance from Junction 1 to the
reference temperature while heat source 2 is heating with P₂. This applies
to R_θJ21 and R_θJ22, respectively.
PNA SUFFIX (PB-FREE)
98ARL10596D
24-PIN PQFN (12 x 12)
Note For package dimensions, refer to
T_J1
T_J2
=
R_θJA11 R_{θJA12 .} P₁
R_θJA21 R_θJA22
P₂
the 35XS3400 data sheet.
The stated values are solely for a thermal performance comparison of
one package to another in a standardized environment. This methodology is not meant to and will not predict the performance
of a package in an application-specific environment. Stated values were obtained by measurement and simulation according to
the standards listed below.
Standards
Table 24. Thermal Performance Comparison
Thermal
Resistance
1 = Power Chip, 2 = Logic Chip [°C/W]
m = 1,
n=1
m = 1, n = 2
m = 2, n = 1
m = 2,
n=2
R_θJAmn ⁽¹⁾⁽²⁾
R_θJBmn ⁽²⁾⁽³⁾
R_θJAmn ⁽¹⁾⁽⁴⁾
R_θJCmn ⁽⁵⁾
27.35
14.53
47.63
1.48
18.40
6.64
37.21
0.00
35.25
23.69
53.61
0.95
Notes:
1. Per JEDEC JESD51-2 at natural convection, still air
condition.
2. 2s2p thermal test board per JEDEC JESD51-7and
JESD51-5.
3. Per JEDEC JESD51-8, with the board temperature on the
center trace near the power outputs.
4. Single layer thermal test board per JEDEC JESD51-3 and
JESD51-5.
5. Thermal resistance between the die junction and the
exposed pad, “infinite” heat sink attached to exposed pad.
0.2mm
0.2mm
0.5mm dia.
Figure 14. Detail of Copper Traces Under Device with
Thermal Vias
35XS3400
40
Analog Integrated Circuit Device Data
Freescale Semiconductor