MC35XS3400 Datasheet, PDF (22/45 Pages) Freescale Semiconductor, Inc – Quad High Side Switch (Quad 35mΩ)

FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
In the event of an external VPWR supply disconnect, an
unexpected current consumption may sink on the VDD
supply pin (In Sleep State). This current leakage is about
70mA instead of 5.0µA and it may impact the device
reliability. The device recovers its normal operational mode
once VPWR is reconnected.
To avoid this unexpected current leakage on the VDD
supply pin, maintain the device in Normal Mode with RST pin
set to logic[1]. This will allow diagnosis of the battery
disconnection event through UV fault reporting in SPI. Then,
apply 0V on VDD supply pin to switch the device to Sleep
State.
NORMAL MODE
The 35XS3400 is in Normal mode when:
• V_PWR and V_DD are within the normal voltage range,
• wake-up = 1,
• fail = 0,
• fault = 0.
In this mode, the NM bit is set to lfault_contrologic [1] and
the outputs HS[0:3] are under control, as defined by hson
signal:
hson[x] = ( ( (IN[x] and DIR_dis[x]) or On bit[x] ) and PWM_en
) or (On bit [x] and Duty_cycle[x] and PWM_en).
In this mode and also in Fail-safe, the fault condition reset
depends on fault_control signal, as defined below:
fault_control[x] = ( (IN_ON[x] and DIR_dis[x]) and PWM_en )
or (On bit [x]).
Programmable PWM module
The outputs HS[0:3] are controlled by the programmable
PWM module if PWM_en and On bits are set to logic [1].
The clock frequency from IN0 input pin or from internal
clock is the factor 2⁷ (128) of the output PWM frequency
(CLOCK_sel bit). The outputs HS[0:3] can be controlled in
the range of 5% to 98% with a resolution of 7 bits of duty cycle
(Table 6). The state of other IN pin is ignored.
Table 6. Output PWM Resolution
On bit
0
1
1
1
1
1
Duty cycle
Output state
X
OFF
0000000
PWM (1/128 duty cycle)
0000001
PWM (2/128 duty cycle)
0000010
PWM (3/128 duty cycle)
n
PWM ((n+1)/128 duty cycle)
1111111
fully ON
The timing includes seven programmable PWM switching
delay (number of PWM clock rising edges) to improve overall
EMC behavior of the light module (Table 7).
Table 7. Output PWM Switching Delay
Delay bits
Output delay
000
no delay
001
16 PWM clock periods
010
32 PWM clock periods
011
48 PWM clock periods
100
64 PWM clock periods
101
80 PWM clock periods
110
96 PWM clock periods
111
112 PWM clock periods
The clock frequency from IN0 is permanently monitored in
order to report a clock failure in case of the frequency is out
a specified frequency range (from f_IN0(LOW) to f_IN0(HIGH)). In
case of clock failure, no PWM feature is provided, the On bit
defines the outputs state and the CLOCK_fail bit reports [1].
Calibratable internal clock
The internal clock can vary as much as +/-30 percent
corresponding to typical f_PWM(0) output switching period.
Using the existing SPI inputs and the precision timing
reference already available to the MCU, the 35XS3400
allows clock period setting within ±10 percent of accuracy.
Calibrating the internal clock is initiated by defined word to
CALR register. The calibration pulse is provided by the MCU.
The pulse is sent on the CS pin after the SPI word is
launched. At the moment, the CS pin transitions from logic [1]
to [0] until from logic [0] to [1] determine the period of internal
clock with a multiplicative factor of 128.
CS
SI
CALR
SI command
ignored
Internal
clock duration
In case of negative CS pulse is outside a predefined time
range (from t _CSB(MIN) to t _CSB(MAX)), the calibration event will
be ignored and the internal clock will be unaltered or reset to
default value (f_PWM(0)) if this was not calibrated before.
The calibratable clock is used, instead of the clock from
IN0 input, when CLOCK_sel is set to [1].
35XS3400
22
Analog Integrated Circuit Device Data
Freescale Semiconductor