MC35XS3400 Datasheet, PDF (30/45 Pages) Freescale Semiconductor, Inc – Quad High Side Switch (Quad 35mΩ)

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
A logic [1] on bit D0 (CSNS_ratio_s) selects the high ratio
on the CSNS pin for the corresponding output. The default
value [0] is the low ratio (Table 14).
Table 14. Current Sense Ratio Selection
CSNS_high_s (D0)
Current Sense Ratio
0
CRS0 (default)
1
CRS1
ADDRESS A₁A₀100 — OUTPUT OVER-CURRENT
REGISTER (OCR)
The OCR_s register allows the MCU to configure
corresponding output over-current protection through the
SPI. Each output “s” is independently selected for
configuration based on the state of the D14 : D13 bits
(Table 11).
D[7:6] bits allow to MCU to programmable bulb cooling
curve and D[5:4] bits inrush curve for selected output, as
shown Table 15 and Table 16.
.
Table 15. Cooling and Inrush Curve Selection
BC1_s (D7)
BC0_s (D6) Profile Curves Speed
0
0
medium (default)
0
1
slow
1
0
fast
1
1
medium
Table 16. Inrush Curve Selection
OC1_s (D5)
OC0_s (D4) Profile Curves Speed
0
0
slow (default)
0
1
fast
1
0
medium
1
1
very slow
A logic [1] on bit D3 (OCHI_s bit) the OCHI1 level is
replaced by OCHI2 during t_OC1, as shown Figure 13.
I_OCH1
I_OCH2
II_OOCC12
I_OC3
I_IOOCC4LO4
II_OOCCLLOO32
I_OCLO1
t_OC1 t_OC3
t _OC2
t _OC4
t _OC5
t _OC6
t _OC7
Time
Figure 13. Over-current profile with OCHI bit set to ‘1’
The wire harness is protected by one of four possible
current levels in steady state, as defined in Table 17.
Table 17. Output Steady State Selection
OCLO1 (D2) OCLO0 (D1)
Steady State Current
0
0
OCLO2 (default)
0
1
OCLO3
1
0
OCLO4
1
1
OCLO1
Bit D0 (OC_mode_sel) allows to select the over-current
mode, as described Table 18.
Table 18. Over-current Mode Selection
OC_mode_s (D0)
Over-current Mode
0
only inrush current management (default)
1
inrush current and bulb cooling management
ADDRESS 00101 — GLOBAL CONFIGURATION
REGISTER (GCR)
The GCR register allows the MCU to configure the device
through the SPI.
Bit D8 allows the MCU to enable or disable the V_DD failure
detector. A logic [1] on VDD_FAIL_en bit allows transitioning
to Fail-safe mode for V_DD < V_DD(FAIL).
Bit D7 allows the MCU to enable or disable the PWM
module. A logic [1] on PWM_en bit allows control of the
outputs HS[0:3] with PWMR register (the direct input states
are ignored).
Bit D6 (CLOCK_sel) allows to select the clock used as
reference by PWM module, as described in the following
Table 19.
35XS3400
30
Analog Integrated Circuit Device Data
Freescale Semiconductor