MC35XS3400 Datasheet, PDF (29/45 Pages) Freescale Semiconductor, Inc – Quad High Side Switch (Quad 35mΩ)

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
DEVICE REGISTER ADDRESSING
The following section describes the possible register
addresses (D[14:10]) and their impact on device operation.
ADDRESS XX000 — STATUS REGISTER
(STATR_S)
The STATR register is used to read the device status and
the various configuration register contents without disrupting
the device operation or the register contents. The register bits
D[4:0] determine the content of the first sixteen bits of SO
data. In addition to the device status, this feature provides the
ability to read the content of the PWMR_s, CONFR0_s,
CONFR1_s, OCR_s, GCR and CALR registers (Refer to the
section entitled Serial Output Communication (Device Status
Return Data) on page 31.
ADDRESS A₁A₀001— OUTPUT PWM CONTROL
REGISTER (PWMR_S)
The PWMR_s register allows the MCU to control the state
of corresponding output through the SPI. Each output “s” is
independently selected for configuration based on the state
of the D14 : D13 bits (Table 11).
Table 11. Output Selection
A₁ (D14)
0
0
1
1
A₀ (D13)
0
1
0
1
HS Selection
HS0 (default)
HS1
HS2
HS3
Bit D7 sets the output state. A logic [1] enables the
corresponding output switch and a logic [0] turns it OFF (if IN
input is also pulled down). Bits D6:D0 set the output PWM
duty-cycle to one of 128 levels for PWM_en is set to logic [1],
as shown Table 6, page 22.
ADDRESS A₁A₀010— OUTPUT CONFIGURATION
REGISTER (CONFR0_S)
The CONFR0_s register allows the MCU to configure
corresponding output switching through the SPI. Each output
“s” is independently selected for configuration based on the
state of the D14 : D13 bits (Table 11).
For the selected output, a logic [0] on bit D5 (DIR_DIS_s)
will enable the output for direct control. A logic [1] on bit D5
will disable the output from direct control (in this case, the
output is only controlled by On bit).
D4:D3 bits (SR1_s and SR0_s) are used to select the high
or medium or low speed slew rate for the selected output, the
default value [00] corresponds to the medium speed slew rate
(Table 12).
Table 12. Slew Rate Speed Selection
SR1_s (D4)
SR0_s (D3)
Slew Rate Speed
0
0
medium (default)
0
1
low
1
0
high
1
1
Not used
Incoming message bits D2 : D0 reflect the desired output
that will be delayed of predefined PWM clock rising edges
number, as shown Table 7, page 22 (only available for
PWM_en bit is set to logic [1]).
ADDRESS A₁A₀011 — OUTPUT CONFIGURATION
REGISTER (CONFR1_S)
The CONFR1_s register allows the MCU to configure
corresponding output fault management through the SPI.
Each output “s” is independently selected for configuration
based on the state of the D14 : D13 bits (Table 11).
A logic [1] on bit D6 (RETRY_unlimited_s) disables the
autoretry counter for the selected output, the default value [0]
corresponds to enable auto-retry feature without time
limitation.
A logic [1] on bit D5 (RETRY_dis_s) disables the auto-
retry for the selected output, the default value [0] corresponds
to enable this feature.
A logic [1] on bit D4 (OS_dis_s) disables the output hard
shorted to VPWR protection for the selected output, the
default value [0] corresponds to enable this feature.
A logic [1] on bit D3 (OLON_dis_s) disables the ON output
open-load detection for the selected output, the default value
[0] corresponds to enable this feature (Table 13).
A logic [1] on bit D2 (OLOFF_dis_s) disables the OFF
output open-load detection for the selected output, the
default value [0] corresponds to enable this feature.
A logic [1] on bit D1 (OLLED_en_s) enables the ON output
open-load detection for LEDs for the selected output, the
default value [0] corresponds to ON output open-load
detection is set for bulbs (Table 13).
Table 13. ON Open-load Selection
OLON_dis_s (D3) OLLED_en_s (D1) ON OpenLoad detection
0
0
enable with bulb threshold
(default)
0
1
enable with LED threshold
1
X
disable
Analog Integrated Circuit Device Data
Freescale Semiconductor
35XS3400
29