MC35XS3400 Datasheet, PDF (20/45 Pages) Freescale Semiconductor, Inc – Quad High Side Switch (Quad 35mΩ)

FUNCTIONAL DEVICE OPERATION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
FUNCTIONAL DEVICE OPERATION
SPI PROTOCOL DESCRIPTION
The SPI interface has a full duplex, three-wire
synchronous data transfer with four I/O lines associated with
it: Serial Input (SI), Serial Output (SO), Serial Clock (SCLK),
and Chip Select (CS).
The SI / SO pins of the 35XS3400 follow a first-in first-out
(D15 to D0) protocol, with both input and output words
transferring the most significant bit (MSB) first. All inputs are
compatible with 5.0V or 3.3V CMOS logic levels.
CCSSB
CS
SCLK
SI
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SO
OD15 OD14 OD13 OD12 OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0
Notes 1. RST is a logic [1] state during the above operation.
NOTES: 1. ^2.R^DST¹B⁵i^:s^Din⁰a^rlo^eg^laic^teH s^totat^te^hd^eur^ming^osth^te^ra^eb^co^eve^ntop^oe^rr^da^etio^rn^e.^{d entry of data into the device.}
2. 3.DO,DD115, D:2O, D...0, arnedlaDt1e5troelathteetofitrhsetm1o6stbreitcsenotfoordredredreedntrfyaouflpt raognrdamstdaatuasintdoathtae LdoUeuXvtiIcoCef.the device.
Figure 9. Single 16-Bit Word SPI Communication
35XS3400
20
Analog Integrated Circuit Device Data
Freescale Semiconductor