MC35XS3400 Datasheet, PDF (28/45 Pages) Freescale Semiconductor, Inc – Quad High Side Switch (Quad 35mΩ)

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
The 35XS3400 successfully meets the Class 5 of the
CISPR25 emission standard and 200V/m or BCI 200mA
injection level for immunity tests.
LOGIC COMMANDS AND REGISTERS
SERIAL INPUT COMMUNICATION
SPI communication is accomplished using 16-bit
messages. A message is transmitted by the MCU starting
with the MSB D15 and ending with the LSB, D0 (Table 9).
Each incoming command message on the SI pin can be
interpreted using the following bit assignments: the MSB,
D15, is the watchdog bit (WDIN). In some cases, output
selection is done with bits D14 : D13. The next three bits,
D12: D10, are used to select the command register. The
remaining nine bits, D8 : D0, are used to configure and control
the outputs and their protection features.
Multiple messages can be transmitted in succession to
accommodate those applications where daisy-chaining is
desirable, or to confirm transmitted data, as long as the
messages are all multiples of 16 bits. Any attempt made to
latch in a message that is not 16 bits will be ignored.
The 35XS3400 has defined registers, which are used to
configure the device and to control the state of the outputs.
Table 10 summarizes the SI registers.
Table 9. SI Message Bit Assignment
Bit Sig
SI Msg Bit
Message Bit Description
MSB
LSB
D15
D14 : D13
D12 : D10
D9
D8:D0
Watchdog in: toggled to satisfy watchdog requirements.
Register address bits used in some cases for output selection (Table 12).
Register address bits.
Not used (set to logic [0]).
Used to configure the inputs, outputs, and the device protection features and SO status content.
Table 10. Serial Input Address and Configuration Bit Map
SI Data
SI
Register
D15
D1
4
D1
3
D1
2
D1
1
D1
0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
STATR_s WDI X X 0 0 0 0 0
0
0
N
0
SOA4
SOA3
SOA2
SOA1
SOA0
PWMR_s WDI A₁ A₀ 0 0 1 0
0
N
ON_s PWM6_s PWM5_s PWM4_s PWM3_s PWM2_s PWM1_s PWM0_s
CONFR0_s WDI A₁ A₀ 0 1 0 0
0
0
N
0
DIR_dis_s SR1_s
SR0_s DELAY2_s DELAY1_s DELAY0_s
CONFR1_s WDI A₁ A₀ 0 1 1 0
0
N
0
Retry_ Retry_dis_s OS_dis_s OLON_dis_s OLOFF_dis_ OLLED_en CSNS_ratio
unlimited_s
s
_s
_s
OCR_s WDI A₁ A₀ 1 0 0 0
0
N
BC1_s BC0_s
OC1_s
OC0_s
OCHI_s
OCLO1_s OCLCO0_s OC_mode_
s
GCR WDI 0 0 1 0 1 0 VDD_F PWM_en CLOCK_sel TEMP_en CSNS_en CSNS1
CSNS0
X
OV_dis
N
AIL_en
CALR WDI 0 0 1 1 1 0 1
0
0
0
1
1
N
0
1
1
Register 0 0 0 X X X 0 0
0
0
0
0
0
state after
RST=0 or
V_DD(FAIL) or
V_SUPPLY(PO
R)
condition
0
0
0
x = Don’t care.
s = Output selection with the bits A₁A₀ as defined in Table 11.
35XS3400
28
Analog Integrated Circuit Device Data
Freescale Semiconductor