33912 Datasheet, PDF (40/47 Pages) Freescale Semiconductor, Inc – LIN System Basis Chip with DC Motor Pre-driver and Current

FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
Timing Control Register - TIMCR
This register is a double purpose register which allows to
configure the watchdog and the cyclic sense periods. Writing
to the Timing Control Register (TIMCR) will also return the
Watchdog Status Register (WDSR).
Table 21. Timing Control Register - $A
C3
C2
C1
C0
Write
CS/WD
WD2
CYST2
WD1
CYST1
WD0
CYST0
Reset
Value
-
0
0
0
Reset
Condition
-
POR
CS/WD - Cyclic Sense or Watchdog prescaler select
This write-only bit selects which prescaler is being written
to, the Cyclic Sense prescaler or the Watchdog prescaler.
1 = Cyclic Sense Prescaler selected
0 = Watchdog Prescaler select
WDx - Watchdog Prescaler
This write-only bits selects the divider for the watchdog
prescaler and therefore selects the watchdog period in
accordance with Table 22. This configuration is valid only if
windowing watchdog is active.
Table 22. watchdog Prescaler
WD2 WD1 WD0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Prescaler Divider
1
2
4
6
8
10
12
14
CYSTx - Cyclic Sense Period Prescaler Select
This write-only bits selects the interval for the wake-up
cyclic sensing together with the bit CYSX8 in the
Configuration Register (CFR) (see page 41).
This option is only active if one of the high side switches is
enabled when entering in Stop or Sleep Mode. Otherwise a
timed wake-up is performed after the period shown in
Table 23.
Table 23. Cyclic Sense Interval
CYSX8⁽⁶⁰⁾ CYST2 CYST1 CYST0
Interval
X
0
0
0
No cyclic sense
0
0
0
1
20ms
0
0
1
0
40ms
0
0
1
1
60ms
0
1
0
0
80ms
0
1
0
1
100ms
0
1
1
0
120ms
0
1
1
1
140ms
1
0
0
1
160ms
1
0
1
0
320ms
1
0
1
1
480ms
1
1
0
0
640ms
1
1
0
1
800ms
1
1
1
0
960ms
1
1
1
1
1120ms
Notes
60. bit CYSX8 is located in Configuration Register (CFR)
Watchdog Status Register - WDSR
This register returns the Watchdog status information and
is also returned when writing to the TIMCR.
Table 24. Watchdog Status Register - $A/$B
S3
S2
S1
S0
Read WDTO WDERR WDOFF WDWO
WDTO - Watchdog Timeout
This read-only bit signals the last reset was caused by
either a watchdog timeout or by an attempt to clear the
Watchdog within the window closed.
Any access to this register or the Timing Control Register
(TIMCR) will clear the WDTO bit.
1 = Last reset caused by watchdog timeout
0 = None
33912
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Analog Integrated Circuit Device Data
Freescale Semiconductor