33912 Datasheet, PDF (14/47 Pages) Freescale Semiconductor, Inc – LIN System Basis Chip with DC Motor Pre-driver and Current

ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 5.5V ≤ V_SUP ≤ 18V, -40°C ≤ T_A ≤ 125°C for the 33912 and -40°C ≤ T_A ≤ 85°C for the
34912, unless otherwise noted. Typical values noted reflect the approximate parameter mean at T_A = 25°C under nominal
conditions, unless otherwise noted.
Characteristic
SPI INTERFACE TIMING (SEE Figure 13, PAGE 20)
Symbol
Min
Typ
Max
Unit
SPI Operating Frequency
SCLK Clock Period
SCLK Clock High Time⁽⁴¹⁾
SCLK Clock Low Time⁽⁴¹⁾
Falling Edge of CS to Rising Edge of SCLK⁽⁴¹⁾
Falling Edge of SCLK to CS Rising Edge⁽⁴¹⁾
MOSI to Falling Edge of SCLK⁽⁴¹⁾
Falling Edge of SCLK to MOSI⁽⁴¹⁾
MISO Rise Time⁽⁴¹⁾
C_L = 220pF
MISO Fall Time⁽⁴¹⁾
C_L = 220pF
Time from Falling or Rising Edges of CS to:⁽⁴¹⁾
- MISO Low-impedance
- MISO High-impedance
Time from Rising Edge of SCLK to MISO Data Valid⁽⁴¹⁾
0.2 x V_DD ≤ MISO ≥ 0.8 x V_DD, C_L = 100pF
f _SPIOP
–
–
4.0
MHz
t_PSCLK
250
–
N/A
ns
t_WSCLKH
110
–
N/A
ns
t_WSCLKL
110
–
N/A
ns
t_LEAD
100
–
N/A
ns
t_LAG
100
–
N/A
ns
t_SISU
40
–
N/A
ns
t_SIH
40
–
N/A
ns
t_RSO
ns
–
40
–
t_FSO
ns
–
40
–
ns
t_SOEN
0.0
–
50
t_SODIS
0.0
–
50
t_VALID
ns
0.0
–
75
RST OUTPUT PIN
Reset Low-level Duration After V_DD High (see Figure 12, page 20)
Reset Deglitch Filter Time
WINDOW WATCHDOG CONFIGURATION PIN (WDCONF)
Watchdog Time Period⁽⁴²⁾
External Resistor R_EXT = 20kΩ (1%)
External Resistor R_EXT = 200kΩ (1%)
Without External Resistor R_EXT (WDCONF Pin Open)
CURRENT SENSE AMPLIFIER⁽⁴¹⁾
t _RST
0.65
1.0
1.35
ms
t _RSTDF
350
600
900
ns
t _PWD
8.5
ms
10
11.5
79
94
108
110
150
205
Common Mode Rejection Ratio
Supply Voltage Rejection Ratio⁽⁴³⁾
CMR
70
–
SVR
60
–
–
dB
–
dB
Gain Bandwidth Product
GBP
0.75
3.0
–
MHz
Output Slew-Rate
SR
0.5
–
–
V/µs
Notes
41. This parameter is guaranteed by process monitoring but not production tested.
42. Watchdog timing period calculation formula: t_PWD [ms] = 0.466 * (R_EXT - 20) + 10 (R_EXT in kΩ)
43. Analog Outputs are supplied by V_DD
33912
14
Analog Integrated Circuit Device Data
Freescale Semiconductor