|
MC9S12HZ128VAL Datasheet, PDF (338/692 Pages) Freescale Semiconductor, Inc – MC9S12HZ256 Data Sheet, Rev. 2.05 | |||
|
◁ |
Chapter 12 Freescaleâs Scalable Controller Area Network (MSCANV2)
2 Reserved bits and unused bits within the TX- and RX-buffers (CANTXFG, CANRXFG) will be read
as âxâ, because of RAM-based implementation.
12.3.2 Register Descriptions
This section describes in detail all the registers and register bits in the MSCAN module. Each description
includes a standard register diagram with an associated ï¬gure number. Details of register bit and ï¬eld
function follow the register diagrams, in bit order. All bits of all registers in this module are completely
synchronous to internal clocks during a register read.
12.3.2.1 MSCAN Control Register 0 (CANCTL0)
The CANCTL0 register provides various control bits of the MSCAN module as described below.
R
W
Reset:
7
RXFRM
0
6
RXACT
5
CSWAI
4
SYNCH
3
TIME
2
WUPE
0
0
0
0
0
= Unimplemented
Figure 12-3. MSCAN Control Register 0 (CANCTL0)
1
SLPRQ
0
0
INITRQ
1
NOTE
The CANCTL0 register, except WUPE, INITRQ, and SLPRQ, is held in the
reset state when the initialization mode is active (INITRQ = 1 and
INITAK = 1). This register is writable again as soon as the initialization
mode is exited (INITRQ = 0 and INITAK = 0).
Read: Anytime
Write: Anytime when out of initialization mode; exceptions are read-only RXACT and SYNCH, RXFRM
(which is set by the module only), and INITRQ (which is also writable in initialization mode).
Table 12-3. CANCTL0 Register Field Descriptions
Field
7
RXFRM1
6
RXACT
5
CSWAI3
Description
Received Frame Flag â This bit is read and clear only. It is set when a receiver has received a valid message
correctly, independently of the ï¬lter conï¬guration. After it is set, it remains set until cleared by software or reset.
Clearing is done by writing a 1. Writing a 0 is ignored. This bit is not valid in loopback mode.
0 No valid message was received since last clearing this ï¬ag
1 A valid message was received since last clearing of this ï¬ag
Receiver Active Status â This read-only ï¬ag indicates the MSCAN is receiving a message. The ï¬ag is
controlled by the receiver front end. This bit is not valid in loopback mode.
0 MSCAN is transmitting or idle2
1 MSCAN is receiving a message (including when arbitration is lost)2
CAN Stops in Wait Mode â Enabling this bit allows for lower power consumption in wait mode by disabling all
the clocks at the CPU bus interface to the MSCAN module.
0 The module is not affected during wait mode
1 The module ceases to be clocked during wait mode
MC9S12HZ256 Data Sheet, Rev. 2.05
338
Freescale Semiconductor
|
▷ |