MC9S12HZ128VAL Datasheet, PDF (128/692 Pages) Freescale Semiconductor, Inc – MC9S12HZ256 Data Sheet, Rev. 2.05

Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.1.6 Port AD Polarity Select Register (PPSAD)
7
R
PPSAD7
W
6
PPSAD6
5
PPSAD5
4
PPSAD4
3
PPSAD3
2
PPSAD2
1
PPSAD1
0
PPSAD0
Reset
0
0
0
0
0
0
0
0
Figure 4-7. Port AD Polarity Select Register (PPSAD)
Read: Anytime. Write: Anytime.
The Port AD Polarity Select Register serves a dual purpose by selecting the polarity of the active interrupt
edge as well as selecting a pull-up or pull-down device if enabled (PERADx = 1). The Port AD Polarity
Select Register is effective only when the corresponding Data Direction Register bit is set to 0 (input).
In pull-down mode (PPSADx = 1), a rising edge on a port AD pin sets the corresponding PIFADx bit. In
pull-up mode (PPSADx = 0), a falling edge on a port AD pin sets the corresponding PIFADx bit.
Table 4-6. PPSAD Field Descriptions
Field
Description
7:0
Polarity Select Port AD
PPSAD[7:0] 0 A pull-up device is connected to the associated port AD pin, and detects falling edge for interrupt generation.
1 A pull-down device is connected to the associated port AD pin, and detects rising edge for interrupt
generation.
4.3.1.7 Port AD Interrupt Enable Register (PIEAD)
R
W
Reset
7
PIEAD7
0
6
PIEAD6
5
PIEAD5
4
PIEAD4
3
PIEAD3
2
PIEAD2
0
0
0
0
0
Figure 4-8. Port AD Interrupt Enable Register (PIEAD)
1
PIEAD1
0
0
PIEAD0
0
Read: Anytime. Write: Anytime.
This register disables or enables on a per pin basis the edge sensitive external interrupt associated with
port AD.
Table 4-7. PIEAD Field Descriptions
Field
Description
7:0
Interrupt Enable Port AD
PIEAD[7:0] 0 Interrupt is disabled (interrupt flag masked).
1 Interrupt is enabled.
MC9S12HZ256 Data Sheet, Rev. 2.05
128
Freescale Semiconductor