MC9S12HZ128VAL Datasheet, PDF (249/692 Pages) Freescale Semiconductor, Inc – MC9S12HZ256 Data Sheet, Rev. 2.05

Chapter 8 Liquid Crystal Display (LCD32F4BV1)
8.4 Functional Description
This section provides a complete functional description of the LCD32F4B block, detailing the operation
of the design from the end user perspective in a number of subsections.
8.4.1 LCD Driver Description
8.4.1.1 Frontplane, Backplane, and LCD System During Reset
During a reset the following conditions exist:
• The LCD32F4B system is configured in the default mode, 1/4 duty and 1/3 bias, that means all
backplanes are used.
• All frontplane enable bits, FP[31:0]EN are cleared and the ON/OFF control for the display, the
LCDEN bit is cleared, thereby forcing all frontplane and backplane driver outputs to the high
impedance state. The MCU pin state during reset is defined by the port integration module (PIM).
8.4.1.2 LCD Clock and Frame Frequency
The frequency of the oscillator clock (OSCCLK) and divider determine the LCD clock frequency. The
divider is set by the LCD clock prescaler bits, LCLK[2:0], in the LCD control register 0 (LCDCR0).
Table 8-7 shows the LCD clock and frame frequency for some multiplexed mode at OSCCLK = 16 MHz,
8 MHz, 4 MHz, 2 MHz, 1 MHz, and 0.5 MHz.
Table 8-7. LCD Clock and Frame Frequency
Oscillator
Frequency in
MHz
OSCCLK = 0.5
OSCCLK = 1.0
OSCCLK = 2.0
OSCCLK = 4.0
OSCCLK = 8.0
OSCCLK = 16.0
LCD Clock Prescaler
LCLK2 LCLK1 LCLK0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
1
0
1
1
1
Divider
1024
2048
2048
4096
4096
8192
8192
16384
16384
32768
65536
131072
LCD Clock
Frequency [Hz]
488
244
488
244
488
244
488
244
488
244
244
122
Frame Frequency [Hz]
1/1 Duty 1/2 Duty 1/3 Duty 1/4 Duty
488
244
163
122
244
122
81
61
488
244
163
122
244
122
81
61
488
244
163
122
244
122
81
61
488
244
163
122
244
122
81
61
488
244
163
122
244
122
81
61
244
122
81
61
122
61
40
31
For other combinations of OSCCLK and divider not shown in Table 8-7, the following formula may be
used to calculate the LCD frame frequency for each multiplex mode:
LCD Frame Frequency (Hz) = ^O-----^S---^C-_D---^C--_i-_v-^L--_i--^Kd---_e---^(r--^H----^z---⁾ ⋅ Duty
The possible divider values are shown in Table 8-7.
MC9S12HZ256 Data Sheet, Rev. 2.05
Freescale Semiconductor
249