MC9S12HZ128VAL Datasheet, PDF (173/692 Pages) Freescale Semiconductor, Inc – MC9S12HZ256 Data Sheet, Rev. 2.05

Chapter 5 Clocks and Reset Generator (CRGV4)
5.3.2.2 CRG Reference Divider Register (REFDV)
The REFDV register provides a finer granularity for the PLL multiplier steps. The count in the reference
divider divides OSCCLK frequency by REFDV + 1.
7
6
5
4
3
2
1
R
0
0
0
0
REFDV3
REFDV2
REFDV1
W
Reset
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 5-5. CRG Reference Divider Register (REFDV)
Read: anytime
Write: anytime except when PLLSEL = 1
NOTE
Write to this register initializes the lock detector bit and the track detector
bit.
0
REFDV0
0
5.3.2.3 Reserved Register (CTFLG)
This register is reserved for factory testing of the CRG module and is not available in normal modes.
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 5-6. CRG Reserved Register (CTFLG)
Read: always reads 0x0000 in normal modes
Write: unimplemented in normal modes
NOTE
Writing to this register when in special mode can alter the CRG
functionality.
MC9S12HZ256 Data Sheet, Rev. 2.05
Freescale Semiconductor
173