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MC9S12HZ128VAL Datasheet, PDF (202/692 Pages) Freescale Semiconductor, Inc – MC9S12HZ256 Data Sheet, Rev. 2.05 | |||
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Chapter 5 Clocks and Reset Generator (CRGV4)
5.6 Interrupts
The interrupts/reset vectors requested by the CRG are listed in Table 5-15. Refer to the device overview
chapter for related vector addresses and priorities.
Table 5-15. CRG Interrupt Vectors
Interrupt Source
Real-time interrupt
LOCK interrupt
SCM interrupt
CCR
Mask
I bit
I bit
I bit
Local Enable
CRGINT (RTIE)
CRGINT (LOCKIE)
CRGINT (SCMIE)
5.6.1 Real-Time Interrupt
The CRG generates a real-time interrupt when the selected interrupt time period elapses. RTI interrupts
are locally disabled by setting the RTIE bit to 0. The real-time interrupt ï¬ag (RTIF) is set to 1 when a
timeout occurs, and is cleared to 0 by writing a 1 to the RTIF bit.
The RTI continues to run during pseudo-stop mode if the PRE bit is set to 1. This feature can be used for
periodic wakeup from pseudo-stop if the RTI interrupt is enabled.
5.6.2 PLL Lock Interrupt
The CRG generates a PLL lock interrupt when the LOCK condition of the PLL has changed, either from
a locked state to an unlocked state or vice versa. Lock interrupts are locally disabled by setting the
LOCKIE bit to 0. The PLL Lock interrupt ï¬ag (LOCKIF) is set to1 when the LOCK condition has
changed, and is cleared to 0 by writing a 1 to the LOCKIF bit.
5.6.3 Self-Clock Mode Interrupt
The CRG generates a self-clock mode interrupt when the SCM condition of the system has changed, either
entered or exited self-clock mode. SCM conditions can only change if the self-clock mode enable bit
(SCME) is set to 1. SCM conditions are caused by a failing clock quality check after power-on reset (POR)
or low voltage reset (LVR) or recovery from full stop mode (PSTP = 0) or clock monitor failure. For details
on the clock quality check refer to Section 5.4.4, âClock Quality Checker.â If the clock monitor is enabled
(CME = 1) a loss of external clock will also cause a SCM condition (SCME = 1).
SCM interrupts are locally disabled by setting the SCMIE bit to 0. The SCM interrupt ï¬ag (SCMIF) is set
to 1 when the SCM condition has changed, and is cleared to 0 by writing a 1 to the SCMIF bit.
MC9S12HZ256 Data Sheet, Rev. 2.05
202
Freescale Semiconductor
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