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MC9S12HZ128VAL Datasheet, PDF (233/692 Pages) Freescale Semiconductor, Inc – MC9S12HZ256 Data Sheet, Rev. 2.05 | |||
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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)
7.3.2.16 ATD Conversion Result Registers (ATDDRx)
The A/D conversion results are stored in 16 read-only result registers. The result data is formatted in the
result registers bases on two criteria. First there is left and right justiï¬cation; this selection is made using
the DJM control bit in ATDCTL5. Second there is signed and unsigned data; this selection is made using
the DSGN control bit in ATDCTL5. Signed data is stored in 2âs complement format and only exists in left
justiï¬ed format. Signed data selected for right justiï¬ed format is ignored.
Read: Anytime
Write: Anytime in special mode, unimplemented in normal modes
7.3.2.16.1 Left Justiï¬ed Result Data
7
R (10-BIT) BIT 9 MSB
R (8-BIT) BIT 7 MSB
6
BIT 8
BIT 6
5
BIT 7
BIT 5
4
BIT 6
BIT 4
3
BIT 5
BIT 3
2
BIT 4
BIT 2
1
BIT 3
BIT 1
W
Reset
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-18. Left Justiï¬ed, ATD Conversion Result Register x, High Byte (ATDDRxH)
0
BIT 2
BIT 0
0
7
6
5
4
3
2
1
0
R (10-BIT) BIT 1
BIT 0
0
0
0
0
0
0
R (8-BIT)
u
u
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
u = Unaffected
Figure 7-19. Left Justiï¬ed, ATD Conversion Result Register x, Low Byte (ATDDRxL)
MC9S12HZ256 Data Sheet, Rev. 2.05
Freescale Semiconductor
233
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