MC9S12HZ128VAL Datasheet, PDF(247/692 Page) Freescale Semiconductor, Inc – MC9S12HZ256 Data Sheet, Rev. 2.05

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MC9S12HZ128VAL Datasheet, PDF (247/692 Pages) Freescale Semiconductor, Inc – MC9S12HZ256 Data Sheet, Rev. 2.05

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Chapter 8 Liquid Crystal Display (LCD32F4BV1)

7

6

5

4

3

2

1

0

R

FP31EN

W

FP30EN

FP29EN

FP28EN

FP27EN

FP26EN

FP25EN

FP24EN

Reset

0

0

0

0

0

0

0

0

Figure 8-7. LCD Frontplane Enable Register 3 (FPENR3)

These bits enable the frontplane output waveform on the corresponding frontplane pin when LCDEN = 1.

Read: anytime

Write: anytime

Table 8-5. FPENR0âFPENR3 Field Descriptions

Field

Description

31:0

FP[31:0]EN

Frontplane Output Enable â The FP[31:0]EN bit enables the frontplane driver outputs. If LCDEN = 0, these

bits have no effect on the state of the I/O pins. It is recommended to set FP[31:0]EN bits before LCDEN is set.

0 Frontplane driver output disabled on FP[31:0].

1 Frontplane driver output enabled on FP[31:0].

8.3.2.4 LCD RAM (LCDRAM)

The LCD RAM consists of 16 bytes. After reset the LCD RAM contents will be indeterminate (I), as

indicated by Figure 8-8.

7

LCDRAM

R

FP1BP3

W

Reset

I

LCDRAM

R

FP3BP3

W

Reset

I

LCDRAM

R

FP5BP3

W

Reset

I

LCDRAM

R

FP7BP3

W

Reset

I

LCDRAM

R

FP9BP3

W

Reset

I

LCDRAM

R

FP11BP3

W

Reset

I

I = Value is indeterminate

6

5

4

3

FP1BP2 FP1BP1 FP1BP0 FP0BP3

I

I

I

I

FP3BP2 FP3BP1 FP3BP0 FP2BP3

I

I

I

I

FP5BP2 FP5BP1 FP5BP0 FP4BP3

I

I

I

I

FP7BP2 FP7BP1 FP7BP0 FP6BP3

I

I

I

I

FP9BP2 FP9BP1 FP9BP0 FP8BP3

I

I

I

I

FP11BP2 FP11BP1 FP11BP0 FP10BP3

I

I

I

I

Figure 8-8. LCD RAM (LCDRAM)

2

FP0BP2

I

FP2BP2

I

FP4BP2

I

FP6BP2

I

FP8BP2

I

FP10BP2

I

1

FP0BP1

I

FP2BP1

I

FP4BP1

I

FP6BP1

I

FP8BP1

I

FP10BP1

I

0

FP0BP0

I

FP2BP0

I

FP4BP0

I

FP6BP0

I

FP8BP0

I

FP10BP0

I

MC9S12HZ256 Data Sheet, Rev. 2.05

Freescale Semiconductor

247

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