MC908JB12DWE Datasheet, PDF(319/332 Page) Freescale Semiconductor, Inc – MC68HC908JB16 Technical Data

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MC908JB12DWE Datasheet, PDF (319/332 Pages) Freescale Semiconductor, Inc – MC68HC908JB16 Technical Data

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Electrical Specifications

Notes:

1. VDD = 4.0 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.

2. Typical values reflect average measurements at midpoint of voltage range, 25 Â°C only.

3. Run (operating) IDD measured using external square wave clock source (fXCLK = 12MHz). All inputs 0.2 V from rail. No dc

loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly

affects run IDD. Measured with all modules enabled.

4. Wait IDD measured using external square wave clock source (fXCLK = 12MHz); all inputs 0.2 V from rail; no dc loads; less

than 100 pF on all outputs. CL = 20 pF on OSC2; 15 kâ¦ Â± 5% termination resistors on D+ and Dâ pins; all ports configured

as inputs; OSC2 capacitance linearly affects wait IDD

5. STOP IDD measured with USB in suspend mode; OSC1 grounded; no port pins sourcing current.

6. Maximum is highest voltage that POR is guaranteed.

7. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum

VDD is reached.

20.7 Control Timing

Characteristic(1)

Symbol

Min

Max

Unit

Internal operating frequency(2)

fOP

â

6

MHz

RST input pulse width low(3)

tIRL

125

â

ns

Notes:

1. VDD = 4.0 to 5.5 Vdc; VSS = 0 Vdc; timing shown with respect to 20% VDD and 70% VDD, unless otherwise noted.

2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this

information.

3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.

20.8 Oscillator Characteristics

Characteristic

Symbol

Min

Crystal frequency(1)

External clock

Reference frequency(1), (2)

fXCLK

1

fXCLK

dc

Crystal load capacitance(3)

CL

â

Crystal fixed capacitance(3)

C1

â

Crystal tuning capacitance(3)

C2

â

Feedback bias resistor

RB

â

Series resistor(3), (4)

RS

â

Notes:

1. The USB module is designed to operate with fXCLK = 12 MHz.

2. No more than 10% duty cycle deviation from 50%.

3. Consult crystal vendor data sheet.

4. Not required for high-frequency crystals.

Typ

12

12

â

2 Ã CL

2 Ã CL

10 Mâ¦

â

Max

12

12

â

â

â

â

â

Unit

MHz

MHz

MC68HC908JB16 â Rev. 1.1

Freescale Semiconductor

Electrical Specifications

Technical Data

319

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