MC908JB12DWE Datasheet, PDF (273/332 Pages) Freescale Semiconductor, Inc – MC68HC908JB16 Technical Data

Input/Output (I/O) Ports
14.5.2 Data Direction Register D
Data direction register D determines whether each port D pin is an input
or an output. Writing a logic 1 to a DDRD bit enables the output buffer for
the corresponding port D pin; a logic 0 disables the output buffer.
Address:
Read:
Write:
Reset:
$0007
Bit 7
0
6
5
4
3
2
1
0
DDRD5 DDRD4 DDRD3 DDRD2 DDRD1
0
0
0
0
0
0
0
Figure 14-9. Data Direction Register D (DDRD)
Bit 0
DDRD0
0
DDRD[5:0] — Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears
DDRD[5:0], configuring all port D pins as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
Port D pins are open-drain when configured as output.
NOTE: Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
NOTE:
For those devices packaged in a 32-pin low-profile quad flat pack,
PTD5–1 are not connected. DDRD5–1 should be set to a 1 to configure
PTD5–1 as outputs.
Figure 14-10 shows the port D I/O circuit logic.
MC68HC908JB16 — Rev. 1.1
Freescale Semiconductor
Input/Output (I/O) Ports
Technical Data
273