MC908JB12DWE Datasheet, PDF (118/332 Pages) Freescale Semiconductor, Inc – MC68HC908JB16 Technical Data

System Integration Module (SIM)
8.8 SIM Registers
The SIM has three memory mapped registers.
• SIM break status register (SBSR)
• SIM reset status register (SRSR)
• SIM break flag control register (SBFCR)
8.8.1 SIM Break Status Register (SBSR)
The SIM break status register contains a flag to indicate that a break
caused an exit from stop or wait mode.
Address: $FE00
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SBSW
R
R
R
R
R
R
R
Write:
Note 1
Reset:
0
Note 1. Writing a logic 0 clears SBSW.
R = Reserved
Figure 8-19. SIM Break Status Register (SBSR)
SBSW — SIM Break Stop/Wait
This status bit is useful in applications requiring a return to wait or stop
mode after exiting from a break interrupt. Clear SBSW by writing a
logic 0 to it. Reset clears SBSW.
1 = Stop mode or wait mode was exited by break interrupt
0 = Stop mode or wait mode was not exited by break interrupt
SBSW can be read within the break state SWI routine. The user can
modify the return address on the stack by subtracting one from it.
The following code is an example of this. Writing 0 to the SBSW bit
clears it.
Technical Data
118
System Integration Module (SIM)
MC68HC908JB16 — Rev. 1.1
Freescale Semiconductor