MC908JB12DWE Datasheet, PDF (119/332 Pages) Freescale Semiconductor, Inc – MC68HC908JB16 Technical Data

System Integration Module (SIM)
;This code works if the H register has been pushed onto the stack in the break
;service routine software. This code should be executed at the end of the break
;service routine software.
HIBYTE EQU
5
LOBYTE EQU
6
;
If not SBSW, do RTI
BRCLR SBSW,SBSR, RETURN
;See if wait mode or stop mode was exited by
;break.
TST
LOBYTE,SP
;If RETURNLO is not zero,
BNE
DOLO
;then just decrement low byte.
DEC
HIBYTE,SP
;Else deal with high byte, too.
DOLO
DEC
LOBYTE,SP
;Point to WAIT/STOP opcode.
RETURN PULH
RTI
;Restore H register.
8.8.2 SIM Reset Status Register (SRSR)
This register contains seven flags that show the source of the last reset.
All flag bits are cleared automatically following a read of the register. The
register is initialized on power-up as shown with the POR bit set and all
other bits cleared. However, during a POR or any other internal reset,
the RST pin is pulled low. After the pin is released, it will be sampled 32
OSCDCLK cycles later. If the pin is not above a V_IH at that time, then the
PIN bit in the SRSR may be set in addition to whatever other bits are set.
Address: $FE01
Bit 7
6
5
4
3
2
1
Bit 0
Read: POR
PIN
COP
ILOP
ILAD
USB
LVI
0
Write:
POR: 1
0
0
0
0
0
0
0
= Unimplemented
Figure 8-20. SIM Reset Status Register (SRSR)
POR — Power-On Reset Bit
1 = Last reset caused by POR circuit
0 = Read of SRSR
MC68HC908JB16 — Rev. 1.1
Freescale Semiconductor
System Integration Module (SIM)
Technical Data
119