MC908JB12DWE Datasheet, PDF (151/332 Pages) Freescale Semiconductor, Inc – MC68HC908JB16 Technical Data

Timer Interface Module (TIM)
10.9 I/O Signals
Port E shares three of its pins with the TIM. PTE0/TCLK is an external
clock input to the TIM prescaler. The two TIM channel I/O pins are
PTE1/T1CH01 and PTE2/T2CH01.
10.9.1 TIM Clock Pin (PTE0/TCLK)
PTE0/TCLK is an external clock input that can be the clock source for
the TIM counter instead of the prescaled internal bus clock. Select the
PTE0/TCLK input by writing logic 1s to the three prescaler select bits,
PS[2:0]. (See 10.10.1 TIM Status and Control Register.) The minimum
TCLK pulse width, TCLK_LMIN or TCLK_HMIN, is:
------------------1-------------------
bus frequency
+
t_SU
The maximum TCLK frequency is:
bus frequency ÷ 2
PTE0/TCLK is available as a general-purpose I/O pin when not used as
the TIM clock input. When the PTE0/TCLK pin is the TIM clock input, it
is an input regardless of the state of the DDRE0 bit in data direction
register E.
10.9.2 TIM Channel I/O Pins (PTE1/T1CH01:PTE2/T2CH01)
Each TIM I/O pin is programmable independently as an input capture pin
or an output compare pin, or configured as buffered output compare or
buffered PWM pins.
MC68HC908JB16 — Rev. 1.1
Freescale Semiconductor
Timer Interface Module (TIM)
Technical Data
151