MC908JB12DWE Datasheet, PDF (127/332 Pages) Freescale Semiconductor, Inc – MC68HC908JB16 Technical Data

Monitor ROM (MON)
If V_TST is applied to IRQ and PTA3 is low upon monitor mode entry
(Table 9-1 condition set 1), the bus frequency is a equal to the external
clock, f_XCLK. If PTA3 is high with V_TST applied to IRQ upon monitor mode
entry (Table 9-1 condition set 2), the bus frequency is a divide-by-two of
the external clock. Holding the PTA3 pin low when entering monitor
mode causes a bypass of a divide-by-two stage at the oscillator only if
V_TST is applied to IRQ. In this event, the OSCOUT frequency is equal to
the OSCDCLK frequency.
Entering monitor mode with V_TST on IRQ, the COP is disabled as long
as V_TST is applied to either the IRQ or the RST. (See Section 8. System
Integration Module (SIM) for more information on modes of operation.)
If entering monitor mode without high voltage on IRQ and reset vector
being blank ($FFFE and $FFFF) (Table 9-1 condition set 3, where IRQ
applied voltage is V_DD), then all port A pin requirements and conditions,
including the PTA3 frequency divisor selection, are not in effect. This is
to reduce circuit requirements when performing in-circuit programming.
Entering monitor mode with the reset vector being blank, the COP is
always disabled regardless of the state of IRQ or the RST.
POR RESET
IS VECTOR NO
BLANK?
YES
MONITOR MODE
EXECUTE
MONITOR
CODE
NORMAL USER
MODE
POR
NO
TRIGGERED?
YES
Figure 9-2. Low-Voltage Monitor Mode Entry Flowchart
MC68HC908JB16 — Rev. 1.1
Freescale Semiconductor
Monitor ROM (MON)
Technical Data
127