MC9S08SG32 Datasheet, PDF (171/328 Pages) Freescale Semiconductor, Inc – HCS08 Microcontrollers

Chapter 11 Internal Clock Source (S08ICSV2)
11.1.2 Features
Key features of the ICS module follow. For device specific information, refer to the ICS Characteristics in
the Electricals section of the documentation.
• Frequency-locked loop (FLL) is trimmable for accuracy using the internal 32 kHz reference over
the specified temperature and voltage ranges
— 0.1% resolution using 9-bit TRIM:FTRIM
— 1.5% deviation for –40 °C to 125 °C standard-temperature rated devices
— 3% deviation for AEC Grade 0 high-temperature rated devices (-40 to 150 °C)
• Internal or external reference clocks up to 5 MHz can be used to control the FLL
— 3-bit select for reference divider is provided
• Internal reference clock has 9 trim bits available
• Internal or external reference clocks can be selected as the clock source for the MCU
• Whichever clock is selected as the source can be divided down
— 2-bit select for clock divider is provided
– Allowable dividers are: 1, 2, 4, 8
– BDC clock is provided as a constant divide by 2 of the DCO output
• Control signals for a low power oscillator as the external reference clock are provided
— HGO, RANGE, EREFS, ERCLKEN, EREFSTEN
• FLL Engaged Internal mode is automatically selected out of reset
11.1.3 Block Diagram
Figure 11-2 is the ICS block diagram.
MC9S08SG32 Data Sheet, Rev. 7
Freescale Semiconductor
171