MC9S08SG32 Datasheet, PDF (131/328 Pages) Freescale Semiconductor, Inc – HCS08 Microcontrollers

Chapter 8 Analog-to-Digital Converter (S08ADC10V1)
the intermediate conversion data is lost. In 8-bit mode, there is no interlocking with ADCRH. If the MODE
bits are changed, any data in ADCRL becomes invalid.
R
W
Reset:
7
ADR7
0
6
ADR6
5
ADR5
4
ADR4
3
ADR3
2
ADR2
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-6. Data Result Low Register (ADCRL)
1
ADR1
0
0
ADR0
0
9.3.5 Compare Value High Register (ADCCVH)
In 10-bit mode, the ADCCVH register holds the upper two bits of the 10-bit compare value (ADCV[9:8]).
When the compare function is enabled, these bits are compared to the upper two bits of the result following
a conversion in 10-bit mode.
In 8-bit operation, ADCCVH is not used during compare.
7
6
5
4
3
2
1
0
R
0
0
0
0
W
ADCV9 ADCV8
Reset:
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-7. Compare Value High Register (ADCCVH)
9.3.6 Compare Value Low Register (ADCCVL)
The ADCCVL register holds the lower eight bits of the 10-bit compare value or all eight bits of the 8-bit
compare value. When the compare function is enabled, bits ADCV[7:0] are compared to the lower eight
bits of the result following a conversion in 10-bit or 8-bit mode.
R
W
Reset:
7
ADCV7
0
6
ADCV6
5
ADCV5
4
ADCV4
3
ADCV3
2
ADCV2
1
ADCV1
0
ADCV0
0
0
0
0
0
0
0
Figure 9-8. Compare Value Low Register (ADCCVL)
9.3.7 Configuration Register (ADCCFG)
ADCCFG selects the mode of operation, clock source, clock divide, and configures for low power and long
sample time.
MC9S08SG32 Data Sheet, Rev. 7
Freescale Semiconductor
121