XR68C192 Datasheet, PDF (9/32 Pages) Exar Corporation – DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER

XR68C92/192
RESET signal or soft-reset by programming the appro-
priate command register. A hardware reset (assertion of
RESET) clears the following registers:
• Status registers A and B (SRA and SRB)
• Interrupt mask register (IMR)
• Interrupt status register (ISR)
• Output port register (OPR)
• Output port configuration register (OPCR)
RESET performs the following operations:
• Initializes the interrupt vector register (IVR) to “0F”
Hex
• Places parallel outputs OP0 through OP7 in the high
state
• Places the counter/timer in timer mode
• Places channels A and B in the inactive state with the
transmitter serial-data outputs (TXA and TXB) in the
mark (high) state.
Software resets are not as encompassing and are
achieved by appropriately programming the channel
A and/or B command registers. Reset commands can
be programmed through the command register to
reset the receiver, transmitter, error status, or break-
change interrupts for each channel
CHIP-SELECT (-CS)
This active-low input signal, when low, enables data
transfers between the CPU and XR68C92/192 on the
data lines (D0 through D7). These data transfers are
controlled by read/write (R/-W) and the register-select
inputs (A1 through A4). When chip-select is high, the
D0 through D7 data lines are placed in the high-
impedance state.
READ/WRITE (R/-W)
When high, this input indicates a read cycle, when low,
it indicates a write cycle. Assertion of the chip-select
input initiates a cycle.
2
DATA TRANSFER ACKOWLEDGE (-DTACK)
This three-state active low output is asserted in read,
write, or interrupt-acknowledge (-IACK) cycles to indi-
cate the proper transfer of data between the CPU and
XR68C92/192. If there is no pending interrupt on an -
IACK cycle, -DTACK is not asserted. At the end of a
transfer, it drives high momentarily, then is three-stated
so that it can be “wire-AND”-ed with other -DTACK
sources, like an open-drain signal.
INTERUPT ACKOWLEDGE (-IACK)
This active-low input indicates an interrupt-acknowl-
edge cycle. If there is an interrupt pending (-INT as-
serted) and this pin is asserted, the XR68C92/192
responds by placing the interrupt vector on the data bus
and then asserting -DTACK. If there is no interrupt
pending (-INT negated), the XR68C92/192 ignores
this signal.
2
REGISTER-SELECT BUS (A1–A4)
The register-select bus lines during read/write opera-
tions select the XR68C92/192 internal registers or
ports.
INTERUPT REQUEST (-INT)
This active-low, open-drain output signals the CPU
that one or more of the eight maskable interrupting
conditions is true.
CHANNEL A/B TRANSMITTER SERIAL-DATA
OUTPUT (TXA/TXB)
The independent transmitter serial-data outputs for
channel A and B transmit the least-significant bit first.
The output is held high (mark condition) when its
associated transmitter is disabled, idle, or operating in
the local loopback mode. (“Mark” is high and “space”
is low). Data is shifted out from this pin on the falling
edge of the programmed clock source.
CHANNEL A/B RECEIVER SERIAL-DATA INPUT
(RXA/RXB)
The independent receiver serial-data inputs for chan-
nel A and B receive the least-significant bit first. Data
on these pins is sampled on the rising edge of the
programmed clock source.
INPUT PORTS (IP0–IP5)
The input ports can be used as general-purpose
inputs. However, each pin also has an alternate
function(s) described below:
IP0
This input can be used as the channel A clear-to-send
active-low input (-CTSA). A change-of-state detector
(Input Port Configuration Register bit-4) is also associ-
ated with this input.
2
IP1
This input can be used as the channel B clear-to-send
active-low input (-CTSB). A change-of-state detector
Rev. P1.10
9