XR68C192 Datasheet, PDF (22/32 Pages) Exar Corporation – DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER

XR68C92/192
programmed by MR1A Bit-6. If programmed as receiver
ready, it is a copy of the SRA Bit-0. If programmed as
FIFO full, it is a copy of the SRA Bit-1.
ISR Bit-2.
Channel A change in break. This bit (when set) indi-
cates that the channel A receiver has detected the
beginning or the end of a break condition. It is reset
when the CPU issues a channel A reset break change
interrupt command.
ISR Bit-3.
Counter/Timer ready. In counter mode, this bit is set
when the counter reaches terminal count. In timer
mode, this bit is set each time the timer output
switches from low to high.
ISR Bit-4.
Transmit ready B. This bit is a duplicate of the channel
B status register transmitter ready bit.
ISR Bit-5.
Receive ready B or FIFO full. The function of this bit
is programmed by MR1B Bit-6. If programmed as
receiver ready, it is a copy of the SRB Bit-0. If
programmed as FIFO full, it is a copy of the SRB Bit-
1.
ISR Bit-6.
Channel B change in break. This bit (when set) indicates
that the channel B receiver has detected the beginning
or the end of a break condition. It is reset when the CPU
issues a channel B reset break change interrupt com-
mand.
ISR Bit-7.
Input port change status. This bit is a “1” when a
change of state has occurred at the IP0, IP1, IP2, or IP3
inputs and that event has been enabled to cause an
interrupt by the programming of ACR Bits 3-0. This bit
is cleared when the CPU reads the input port change
register.
INTERRUPT MASK REGISTER (IMR)
This register selects which bits in the interrupt status
register can cause an interrupt output. If a bit in the
interrupt status register is a “1” and the corresponding
bit in this register is also a “1”, the -INT output will be
asserted. If the corresponding bit in this register is a
zero, the state of the bit in the interrupt status register
has no effect on the -INT output. Note that the interrupt
mask register does not mask the programmable inter-
rupt outputs OP7 through OP3 or the value read from
the interrupt status register.
IMR Bit-0.
0 = Normal, no interrupt.
1 = Enable channel A transmit ready interrupt.
IMR Bit-1.
0 = Normal, no interrupt.
1 = Enable channel A receive ready or FIFO full
interrupt. RxRDY or FIFO-full is selected via MR1A
Bit-6.
IMR Bit-2.
0 = Normal, no interrupt.
1 = Enable channel A received break signal interrupt.
IMR Bit-3.
0 = Normal, no interrupt.
1 = Enable Timer/Counter interrupt.
IMR Bit-4.
0 = Normal, no interrupt.
1 = Enable channel B transmit ready interrupt.
IMR Bit-5.
0 = Normal, no interrupt.
1 = Enable channel B receive ready or FIFO full
interrupt. RxRDY or FIFO-full is selected via MR1B Bit-
6.
IMR Bit-6.
0 = Normal, no interrupt.
1 = Enable channel B received break signal interrupt.
IMR Bit-7.
0 = Normal, no interrupt.
1 = Enable input port state change interrupt.
INPUT PORT REGISTER
State of the input ports (IP0-IP6) can be read via this
register.
IPR Bit 0-6.
0 = Inputs are in low state.
1 = Inputs are in high state.
Rev. P1.10
22