XR68C192 Datasheet, PDF (19/32 Pages) Exar Corporation – DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER

XR68C92/192
Baud Rate Table (based on a 3.6864MHz clock)
MR0 Bits
2,0=0
MR0 Bit-0=1
(extended 1)
MR0 Bit-2=1
(extended 2)
CSR
A/B
SET-1
ACR
Bit-7=0
SET-2
ACR
Bit-7=1
SET-1
ACR
Bit-7=0
SET-2
ACR
Bit-7=1
SET-1
ACR
Bit-7=0
SET-2
ACR
Bit-7=1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
50
110
134.5
200
300
600
1200
1050
2400
4800
7200
9600
38.4k
Timer
IP4-16X
IP4-1X
75
110
134.5
150
300
600
1200
2000
2400
4800
1800
9600
19.2k
Timer
IP4-16X
IP4-1X
300
110
134.5
1200
1800
3600
7200
1050
14.4k
28.8k
7200
57.6k
230.4k
Timer
IP4-16X
IP4-1X
450
110
134.5
900
1800
3600
7200
2000
14.4k
28.8k
1800
57.6k
115.2k
Timer
IP4-16X
IP4-1X
4800
680
1076
19.2k
28.8k
57.6k
115.2k
1050
57.6k
4800
57.6k
9600
38.4k
Timer
IP4-16X
IP4-1X
7200
680
1076
14.4k
28.8k
57.6k
115.2k
2000
57.6k
4800
14.4k
9600
19.2k
Timer
IP4-16X
IP4-1X
1 01 0 = Set Timeout Mode On. The receiver in this
channel will restart the C/T as each receive
character is transferred from the shift register
to the receive FIFO. The C/T is placed in the
counter mode, the START/STOP counter
commands are disabled, the counter is
stopped, and the Counter Ready Bit, ISR Bit-
3 is reset. (See also Watchdog timer de-
scription in the receiver section.)
1 0 1 1 = Set MR pointer to MR0.
1 1 0 0 = Disable Timeout Mode. This command re-
turns control of the C/T to the regular Start/
Stop counter commands. It does not stop the
counter, or clear any pending interrupts.
After disabling the timeout mode, a “Stop
Counter” command should be issued to force
a reset of the ISR Bit-3.
1 1 0 1 = Not used.
1 1 1 0 = Power Down Mode On. In this mode, the
DUART oscillator is stopped and all func-
tions requiring this clock are suspended. The
execution of commands other than disable
power down mode (1111) requires a XTAL1.
While in the power down mode, do not issue
any commands to the CR A/B except the
disable power down mode command. The
contents of all registers will be saved while in
this mode. It is recommended that the trans-
mitter and receiver be disabled prior to plac-
ing the DUART into power down mode. This
command is in CRA only.
1 1 1 1 = Disable Power Down Mode. This command
restarts the oscillator. After invoking this
command, wait for the oscillator to start up
before writing further commands to the CR A/
B. This command is in CRA only. For maxi-
mum power reduction input pins should be at
GND or VCC.
STATUS REGISTER (SRA/SRB)
SR A/B Bit-0.
Receive Ready.
This bit indicates that one or more character(s) has
been received and is waiting in the FIFO for the CPU to
read it. It is set when the first character is transferred
Rev. P1.10
19