XR68C192 Datasheet, PDF (12/32 Pages) Exar Corporation – DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER

XR68C92/192
error, the damaged character is transferred to a holding
register with the framing error flag set. If the receiver
serial data remains low for one-half of the bit period after
the stop bit was sampled, the receiver operates as if a
new start bit transition has been detected. If the stop bit
is 0 and the data and parity (if any) are also all zero, it
is a break. A character consisting of all zeros will be
loaded into a receive holding register (RHR) with the
received-break bit (but not the framing error bit) set to
one. The receiver serial-data input must return to a high
condition for at least one-half bit time before a search for
the next start bit begins.
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The receiver can detect a break that starts in the
middle of a character provided the break persists
completely through the next character time or longer.
When the break begins in the middle of a character,
the receiver will place the damaged character in a
holding register with the framing error bit set. Then,
provided the break persists through the next character
time, the receiver will also place an all-zero character
in the next holding register with the received-break bit
set. The parity error, framing error, overrun error, and
received-break conditions (if any) set error and break
flags in the status register at the received character
boundary and are valid only when the receiver-ready
bit (RxRDY) in the status register is set. A first-in first-
out (FIFO) stack is used in each channels receive
buffer logic and consists of 8 (16 for XR68C192) receive
holding registers.
The receiver buffer is composed of the FIFO and a
receive shift register connected to the receiver serial-
data input. Data is assembled in the shift register and
loaded into the top most empty FIFO receive holding
register position. The receiver-ready bit in the status
register (SRA or SRB) is set whenever one or more
characters are available to be read. A read of the
receiver buffer produces an output of data from the top
of the FIFO stack. After the read cycle, the data at the
top of the FIFO stack and its associated status bits are
“popped” and new data can be added at the bottom of
the stack by the receive shift register. The FIFO-full
status bit is set if all eight stack positions are filled with
data. Either the receiver-ready or the FIFO-full status
bits can be selected to cause an interrupt. In addition
to the data byte, three status bits (parity error, framing
error, and received break) are appended to each data
character in the FIFO (overrun is not). By program-
ming the error-mode control bit in the mode register,
status can be provided for “character” or “block” modes.
In the “character” mode, the status register (SRA or
SRB) is updated on a character-by-character basis and
applies only to the character at the top of the FIFO.
Thus, the status must be read before the character is
read. Reading the character pops it and its error flags
off the FIFO. In the “block” mode, the status provided
in the status register for the parity error, framing error,
and received-break conditions are the logical OR of
these respective bits, for all characters coming to the
top of the FIFO stack since the last reset error com-
mand was issued. That is, starting at the last reset-error
command, a continuous logical-OR function of corre-
sponding status bits is produced in the status register
as each character comes to the top of the FIFO stack.
The block mode is useful in applications requiring the
exchange of blocks of information where the software
overhead of checking each characters error flags
cannot be tolerated. In this mode, entire messages
can be received and only one data integrity check is
performed at the end of each message. Although data
reception in this manner has speed advantages, there
are also disadvantages. Because each character is
not individually checked for error conditions by the
software, if an error occurs within a message the error
will not be recognized until the final check is per-
formed. Also, there is no indication of which
character(s) is in error within the message.
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Reading the status register (SR) does not affect the
FIFO. The FIFO is “popped” only when the receive
buffer is read. If all 8/16 of the FIFOs receive holding
registers are full when a new character is received, that
character is held in the receive shift register until a FIFO
position is available. If an additional character is re-
ceived while this state exists, the contents of the FIFO
are not affected, but the character previously in the shift
register is lost and the overrun-error status bit will be set
upon receipt of the start bit of the new overrunning
character.
To support flow control, a receiver can automatically
negate and reassert the request-to-send (RTS) output
(alternate function of output ports OP0 and OP1). The
request-to-send output will automatically be negated
by the receiver when a valid start bit is received and the
FIFO stack is full. When a FIFO position becomes
available, the request-to-send output will be reasserted
Rev. P1.10
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