XR68C192 Datasheet, PDF (4/32 Pages) Exar Corporation – DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER

XR68C92/192
SYMBOL DESCRIPTION (* 44 TQFP Package)
Symbol
-DTACK
RX A/B
TX A/B
OP0
OP1
OP2
OP3
OP4
Pin
Signal
44 40 44* type
Pin Description
10
9
4
O Data transfer acknowledge (three-state active low output).
During Read, Write, or interrupt cycle goes low to indicate
proper transfer of data between the CPU and XR68C92/
192.
35,11 31,10 29,5 I Serial data input. The serial information (data) received
from serial port to XR68C92/192 receive input circuit. A
mark (high) is logic one and a space (low) is logic zero.
33,13 30,11 28,6 O Serial data output. The serial data is transmitted via this pin
with additional start , stop and parity bits. The TX will be held
in mark (high) state during reset, local loop back mode or
when the transmitter is disabled.
32 29 27
O Multi-purpose output. General purpose output or Channel A
Request-To-Send (-RTSA active low).
14 12
7
O Multi-purpose output. General purpose output or Channel B
Request-To-Send (-RTSB active low).
31 28 26
O Multi-purpose output. General purpose output or one of the
following functions can be selected for this output pin by
programming the Output Port Configuration Register bits 1,0:
TxAClk1 -Transmit 1X clock.
TxAClk16 -Transmit 16X clock
RxAClk1 -Receive 1X clock
15 13
8
O Multi-purpose output. General purpose output or one of the
following functions can be selected for this output pin by
programming the Output Port Configuration Register bits 3,2:
C/T -Counter timer output (Open drain output)
TxBClk1 -Transmit 1X clock
RxBClk1 -Receive 1X clock
30 27 25
O Multi-purpose output. General purpose output or one of the
following functions can be selected for this output pin by
programming the Output Port Configuration Register bit 4:
-RxARDY -Receive ready signal (Open drain output)
-RxAFULL - Receive FIFO full signal (Open drain output)
Rev. P1.10
4