XR68C192 Datasheet, PDF (10/32 Pages) Exar Corporation – DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER

XR68C92/192
(IPCR bit-5) is also associated with this input.
IP2
This input can be used as the channel B receiver
external clock input (RxBClk1), or the counter/timer
external clock input. When this input functions as the
external clock to the receiver, the received data is
sampled on the rising edge of the clock. A change-of-
state detector (IPCR bit-6) is also associated with this
input.
IP3
This input can serve as the channel A transmitter
external clock input (TxAClk1). When this input func-
tions as the external clock to the transmitter, the
transmitted data is clocked on the falling edge of the
clock. A change-of-state detector (IPCR bit-7) is also
associated with this input.
IP4
This input can be used as the channel A receiver
external clock input (RxAClk1). When this input func-
tions as the external clock to the receiver, the received
data is sampled on the rising edge of the clock.
IP5
This input can serve as the channel B transmitter
external clock (TxBClk1). When this input is used as
the external clock to the transmitter, the transmitted
data is clocked on the falling edge of the clock.
OUTPUT PORTS (OP0–OP7)
The output ports can be used as general-purpose
outputs however, each pin also has an alternate
function(s), described below.
OP0
This output can function as the channel A transmitter
active-low request-to-send output, or as the channel A
receiver active-low request-to-send (-RTSA) output.
This pin, if asserted by programming the corresponding
bit in OPCR, is used by the transmitter (MRA2 bit-5 =
1) to indicate end of transmission by negating it. This
is useful because, even when a command to disable the
transmitter is sent before the data is fully transmitted,
the transmitter sends all the data, negates OP0 and
then gets disabled. When used by the receiver (MRA1
bit-7 = 1), this pin is automatically negated and reas-
serted depending on the FIFO space available.
OP1
This output is identical to OP0 and is meant for channel
B of the DUART.
2
OP2
This output can be programmed (bits 0 & 1 of OPCR) to
represent the channel A transmitter 1X-clock or 16X-
clock output or the channel A receiver 1X-clock output.
OP3
This output can be used (when bits 2 & 3 of OPCR are
programmed) as the open-drain active-low counter-
ready output, the open-drain timer output, the channel
B transmitter 1X-clock output, or the channel B receiver
1X-clock output.
OP4
This output, when programmed using bit-4 of OPCR,
can serve as the channel A open-drain active-low
receiver-ready or buffer-full interrupt outputs (RxARDY/
RxAFULL). One of RxARDY or RxAFULL can be se-
lected using bit-6 of MRA1.
OP5
This output, when programmed using bit-5 of OPCR can
be used as the channel B open-drain active-low receiver-
ready or buffer-full interrupt outputs (RxRDYB/
RxBFULL). One of RxBRDY or RxBFULL can be se-
lected using bit-6 of MRB1.
OP6
This output can function as the channel A open-drain
active-low transmitter-ready interrupt output
(TxARDY).
OP7
This output can serve as the channel B open-drain
active-low transmitter-ready interrupt output (TxBRDY).
TRANSMITTER
The channel A and B transmitters are enabled for data
transmission through their respective command reg-
isters. The XR68C92/192 signals the CPU that it is
ready to accept a character by setting the transmitter-
ready bit in the channel's status register. Users can
program this condition to generate an interrupt re-
quest on the -INT output, an interrupt request for channel
A’s transmitter on parallel output OP6, or for channel
B’s transmitter on parallel output OP7. When a charac-
ter is loaded into the transmit buffer, the above condition
Rev. P1.10
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