XR68C192 Datasheet, PDF (6/32 Pages) Exar Corporation – DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER

XR68C92/192
SYMBOL DESCRIPTION (* 44 TQFP Package)
Symbol
IP2
IP3
IP4
IP5
-IACK
-CS
D0-D7
Pin
Signal
44 40 44* type
active low).
Pin Description
40 36 34
I Multi-purpose input or Timer/Counter External clock input.
3
2
41
I Multi-purpose input or Channel A transmit external clock
input. The transmit data is clocked on the falling edge of the
clock.
43 39 37
I Multi-purpose input or Channel A receive external clock
input. The received data is clocked on the rising edge of the
clock.
42 38 36
I Multi-purpose input or Channel B Transmit external clock
input. The transmit data is clocked on the falling edge of the
clock.
41 37 35
I Interrupt acknowledge (active low). Indicating an interrupt
acknowledge cycle. XR68C92/192 will place the interrupt
vector on the data bus and will set -DTACK low if it has a
pending interrupt.
39 35 33
I Chip select (active low). A low at this pin enables the serial
port / CPU data transfer operation.
28,18 25,16 22,12
Bi-directional data bus. Eight bit, three state data bus to
27,19 24,17 21,13 I/O transfer information to or from the CPU. D0 is the least
26,20 23,18 20,14
significant bit of the data bus and the first serial data bit to be
25,21 22,19 19,15
received or transmitted.
R/-W
VCC
N.C.
9
8
3
I Read/Write strobe. When -CS is asserted, a high level on this
pin transfers the contents of the XR68C92/192 data bus to
the CPU, and a low level on this pin will transfer the contents
of the CPU data bus to the addressed register.
44 40 38,39 Pwr Power supply input.
1,12
23,34
11,23
No Connection.
Rev. P1.10
6