XR68C192 Datasheet, PDF (20/32 Pages) Exar Corporation – DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER

XR68C92/192
from the receive shift register to the empty FIFO, and
cleared when the CPU reads the receiver buffer, if there
are no more characters in the FIFO after the read.
SR A/B Bit-1.
Receive FIFO Full.
This bit is set when a character is transferred from the
receive shift register to the receiver FIFO and the
transfer fills the FIFO. All eight FIFO holding register
positions are occupied. It is cleared when the CPU
reads the receiver buffer, unless a ninth character is in
the receive shift register waiting for an empty FIFO slot.
SR A/B Bit-2.
Transmit Ready.
This bit (when set) indicates that the transmit holding
register is empty and ready to be loaded with a charac-
ter. Transmitter ready is set when the character is
transferred to the transmit shift register. This bit is
cleared when the CPU loads the transmit holding
register, or when the transmitter is disabled.
SR A/B Bit-3.
Transmit Empty.
This bit will be set when the channel A/B transmitter
under-runs (empty). Both the transmit holding register
and the transmit shift register are empty. It is set after
transmission of the last stop bit of a character if no
character is in the transmit holding register awaiting
transmission. It is cleared when the CPU loads the
transmit holding register or when the transmitter is
disabled.
SR A/B Bit-4.
Overrun Error.
This bit (when set) indicates one or more characters in
the received data stream have been lost. It becomes set
on receipt of a valid start bit when the FIFO is full and a
character is already in the receive shift register waiting
for an empty FIFO position. When this occurs, the
character in the receive shift register (and its break
detect, parity error, and framing error status, if any) is
lost. A reset error status command clears this bit.
SR A/B Bit-5.
Parity Error.
This bit becomes set when the “with parity” or “force
parity” mode is programmed by mode register one and
the corresponding character in the FIFO is received with
incorrect parity. In the Multidrop mode, the parity error
bit position stores the received address/data bit. This bit
is valid only when the RxRDY bit is set (SR A/B Bit-0 =
1).
SR A/B Bit-6.
Framing Error.
This bit (when set) indicates that a stop bit was not
detected when the corresponding data character in the
FIFO was received. The stop bit check is made in the
middle of the first stop bit position. This bit is valid only
when the RxRDY bit is set (SR A/B Bit-0 = 1). Framing
error and break are exclusive: At least one data bit and/
or the parity bit must have been a 1 to signal a framing
error. After a framing error, the receiver does not wait for
the line to return to the marking state (high), if the line
remains low for 1/2 a bit time after the stop bit sample
(that is, the nominal end of the first stop bit), the receiver
treats it as the beginning of a new start bit.
SR A/B Bit-7.
Received Break.
This bit indicates an all-zero character of the pro-
grammed length has been received without a stop bit.
This bit is valid only when the RxRDY bit is set (SR A/
B Bit-0 = 1). Only a single FIFO position is occupied
when a break is received, additional entries to the
FIFO are inhibited until the channel A/B receiver serial
data input line returns to the marking state. The break-
detect circuitry can detect a break that starts in the
middle of a received character, however, the break
condition must persist completely through the end of
the current character and the next character time to be
recognized.
OUTPUT PORT CONFIGURATION REGISTER
(OPCR)
This register selects following options for output
ports.4Alternate functions of OP1 and OP0 are con-
trolled by the mode registers, not the OPCR. MR1A Bit-
7 and MR2A Bit-5 control OP0, MR1B Bit-7 and MR2B
Bit-5 control OP1.
OP2 output select
0 0 = The complement of OPR
0 1 = TxAClk16-Transmit A 16X clock
1 0 = TxAClk1-Transmit A 1X clock
1 1 = RxAClk1- Receive A 1X clock
Rev. P1.10
20