XR68C192 Datasheet, PDF (23/32 Pages) Exar Corporation – DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER

IPR Bit-7.
Not used and set to “0”.
COUNTER REGISTER (CUR and CLR)
The count upper register (CUR) and count lower
register (CLR) hold the most-significant byte and the
least-significant byte, respectively, of the current
counter value. These registers should only be read
when the C/T is in counter mode and the counter is
stopped.
START COUNTER / TIMER REGISTER
Reading from this register will start Timer counter
function. Returned data values should be ignored.
STOP COUNTER TIMER REGISTER
Reading from this register will issue a stop command to
Timer counter function. Returned data values should be
ignored.
SET OUTPUT PORT REGISTER
Output ports (OP0-OP7) can be set to low by writing a
“1” to each individual bits. Outputs will change state only
when OPCR register bits are assigned to general
purpose output pins. When output is set to low, it can
not change state to high unless reset output port
command is issued.
SOPR Bit 0-7.
0 = No change.
1 = Set output port to low.
RESET OUTPUT PORT BITS REGISTER
Each output port bit can be changed to high state by
writing a “1” to each individual bit.
SOPR Bit 0-7.
0 = No change.
1 = Reset output port to high.
4
INTERRUPT VECTOR REGISTER (IVR)
This register contains the interrupt vector. When the
XR68C92 responds to a valid interrupt acknowledge (-
IACK) cycle, the contents of this register are placed on
the data bus. At reset, this register will contain “0F” hex,
which is the M68000 exception vector assignment for
un-initialized interrupt vectors.
Rev. P1.10
23
XR68C92/192