XR68C192 Datasheet, PDF (5/32 Pages) Exar Corporation – DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER

XR68C92/192
SYMBOL DESCRIPTION (* 44 TQFP Package)
Symbol
OP5
OP6
OP7
A1-A4
XTAL1
XTAL2
-RESET
GND
-INT
IP0
IP1
Pin
Signal
44 40 44* type
Pin Description
16 14
9
O Multi-purpose output. General purpose output or one of the
following functions can be selected for this output pin by
programming the Output Port Configuration Register bit 5:
-RxBRDY - Receive ready signal (Open drain output)
-RxBFULL - Receive FIFO full signal (Open drain output)
29 26 24
O Multi-purpose output. General purpose output or Transmit
A holding register empty interrupt (-TxARDY Open drain
output).
17 15 10
O Multi-purpose output. General purpose output or Transmit
B holding register empty interrupt (-TxBRDY Open drain
output).
2,4, 1,3, 40,42,
6,7 5,6 44,1 I
Address select lines. To select internal registers.
36 32 30
I Crystal input 1 or external clock input. A crystal can be
connected to this pin and XTAL2 pin to utilize the internal
oscillator circuit. An external clock can be used to clock
internal circuit and baud rate generator for custom transmis-
sion rates.
37
33
31
O Crystal input 2 or buffered clock output. See XTAL1.
38 34 32
I Master reset. (active low) A low on this pin will reset all the
outputs and internal registers. The transmitter output and
the receiver input will be disabled during reset time.
22 20 16,17 Pwr Signal and power ground.
24
21
18
O Interrupt output (open drain active low) This pin goes low upon
occurrence of one or more of eight maskable interrupt condi-
tions (when enabled by the interrupt mask register) . CPU can
read the interrupt status register to determine the interrupting
condition(s). This output requires a pull-up resistor.
8
7
2
I Multi-purpose input or Channel A Clear-To-Send (-CTSA
active low).
5
4
43
I Multi-purpose input or Channel B Clear-To-Send (-CTSB
Rev. P1.10
5