XR68C192 Datasheet, PDF (13/32 Pages) Exar Corporation – DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER

XR68C92/192
automatically by the receiver. Connecting the request-
to-send output to the clear-to-send (CTS) input of a
transmitting device, prevents overrun errors in the re-
ceiver. The RTS output must be manually asserted the
first time. Thereafter, the receiver will control the RTS
output.
If the FIFO stack contains characters and the receiver
is then disabled, the characters in the stack can still be
read but no additional characters can be received until
the receiver is again enabled. If the receiver is dis-
abled while receiving a character, or while there is a
character in the shift register waiting for a FIFO
opening, these characters are lost. If the receiver is
reset, the FIFO stack and all of the receiver status bits,
the corresponding output ports, and the interrupt
request are reset. No additional characters can be
received until the receiver is again enabled.
LOOPBACK MODES
Besides the normal operation mode in which the
receiver and transmitter operate independently, each
XR68C92/192 channel can be configured to operate in
various looping modes that are useful for local and
remote system diagnostic functions.
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AUTOMATIC ECHO MODE
In this mode, the channel automatically retransmits
the received data on a bit-by-bit basis. The local CPU-
to-receiver communication continues normally but
the CPU-to-transmitter link is disabled.
LOCAL LOOPBACK MODE
In this mode, the transmitter output is internally con-
nected to the receiver input. The external TX pin is
held in the mark (high) state in this mode. This mode
is useful for testing the operation of a local XR68C92/
192 channel. By sending data to the transmitter and
checking that the data assembled by the receiver is
the same data that was sent, proper channel operation
can be ensured. In this mode the CPU-to-transmitter
and CPU-to-receiver communications continue nor-
mally.
REMOTE LOOPBACK MODE
In this mode, the channel automatically retransmits the
received data on a bit-by-bit basis. The local CPU-to-
receiver and CPU-to-transmitter links are disabled. This
mode is useful in testing the receiver and transmitter
operation of a remote channel. This mode requires the
remote channel receiver to be enabled.
MULTIDROP MODE
Users can program the channel to operate in a wake-up
mode for Multidrop applications. This mode is selected
by setting bits 3 & 4 in Mode Register 1 (MR1). In this
mode of operation, a master station channel, connected
to several slave stations (a maximum of 256 unique
slave stations), transmits an address character fol-
lowed by a block of data characters targeted for one or
more of the slave stations. In this mode, the channel
receivers within the slave stations are disabled, but they
continuously monitor the data stream sent out from the
master station. When the slave stations channel receiv-
ers detect any address character in the data stream,
each receiver notifies its respective CPU by setting
receiver ready (RXRDY) and generating an interrupt, if
programmed to do so. Each slave station CPU then
compares the received address to its station address
and enables its receiver if it wants to receive the
subsequent data from the master station.
Slave stations that are not addressed continue moni-
toring the data stream for the next address character.
An address character flags the end of one block of data
and the start of another. After receiving a block of
data, the slave stations CPU may disable the channel
receiver and re-initiate the process. A transmitted
character from the master station consists of a start
bit, the programmed number of data bits, an address/
data (A/D) bit flag, and the programmed number of
stop bits. The address/data bit identifies to the slave
stations channel whether the character should be
interpreted as an address character or a data charac-
ter. The character is interpreted as an address charac-
ter if the A/D bit is set to a one or interpreted as a data
character if it is set to a zero. The polarity of the
transmitted address/data bit is selected by program-
ming bit two in Mode Register 1 (MR1) to a '1' for an
address character and to a '0' for data characters. Users
should program the mode register prior to loading the
corresponding data or address characters into the
transmit buffer.
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In the Multidrop mode, the receiver continuously
monitors the received data stream regardless of
whether it is enabled or disabled. If the receiver is
disabled, it sets the receiver ready status bit and loads
the character into the FIFO receive holding register
stack provided the received address/data bit is a one
Rev. P1.10
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