XR68C192 Datasheet, PDF (21/32 Pages) Exar Corporation – DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER

XR68C92/192
OP3 output select
0 0 = The complement of OPR
0 1 = C/T Output 1
1 0 = TxBClk1-Transmit B 1X clock
1 1 = RxBClk1- Receive B 1X clock
If OP3 is to be used for the timer output, Users should
program the counter/timer for timer mode (ACR Bit-6
= 1), initialize the counter/timer pre-load registers
(CTUR and CTLR), and the start counter command
issued before setting OPCR Bits 3-2 = 01.
OP4 output select
0 = The complement of OPR
1 = -RxARDY/-RxAFULL
OP5 output select
0 = The complement of OPR
1 = -RxBRDY/-RxBFULL
OP6 output select
0 = The complement of OPR
1 = -TxARDY
OP7 output select
0 = The complement of OPR
1 = -TxBRDY
Output Port Register (OPR)
All bits, unless programmed for alternate function, can
be set high or low individually:
0 = Sets output port high
1 = Sets output port low
For example, setting bit-4 to 1 will set OP4 low.
AUXILIARY CONTROL REGISTER (ACR)
ACR Bits 3-0.
This field selects which bits of the input port change
register (IPCR) cause the input change bit in the
interrupt status register (ISR Bit-7) to be set.
0 = Disabled
1 = Enabled
ACR Bits 6-4.
Counter/Timer Mode and Clock Source. Should only be
altered while the C/T is not in use (stopped if in counter
mode, output and/or interrupt masked if in timer mode).
MODE CLOCK
SOURCE
000
001
010
011
100
101
110
111
Counter
Counter
Counter
Counter
Timer
Timer
Timer
Timer
External (IP2)
TXAClk1-Transmit A 1X clock
TXBClk1-Transmit B 1X clock
Crystal or External Clock
(XTAL1/Clk) Divided by 16
External (IP2)
External (IP2) Divided by 16
Crystal or External Clock
(XTAL1/Clk)
Crystal or External Clock
(XTAL1/Clk) Divided by 16
ACR Bit-7
Baud rate table Select. Should only be changed after
both channels have been reset and are disabled.
0 = Set 1
1 = Set 2
INPUT PORT CHANGE REGISTER (IPCR)
IP Level Bits 3-0.
0 = Low
1 = High
IP Delta Bits 7-4.
0 = No
1 = Yes
INTERRUPT STATUS REGISTER (ISR)
This register provides the status of all potential interrupt
sources. The contents of this register are logically
“AND”-ed with the contents of the interrupt mask regis-
ter, and the results are "NOR"-ed to produce the -INT
output. All active interrupt sources are visible by reading
the ISR, regardless of the contents of the interrupt mask
register. Reading the ISR has no effect on any interrupt
source. Each active interrupt source must be cleared in
a source-specific fashion to clear the ISR. All interrupt
sources are cleared when the XR68C92/192 is reset.
4
ISR Bit-0.
Transmit ready A. This bit is the channel A equivalent of
ISR Bit-4.
ISR Bit-1.
Receive ready A or FIFO full. The function of this bit is
Rev. P1.10
21