XR16C850CM-F Datasheet, PDF (7/56 Pages) Exar Corporation – 2.97V TO 5.5V UART WITH 128-BYTE FIFO

xr
REV. 2.3.1
XR16C850
2.97V TO 5.5V UART WITH 128-BYTE FIFO
NAME
OP1#/
RS485
RESET
VCC
GND
44-PIN
PLCC
48-PIN
TQFP
TYPE
DESCRIPTION
38
34 O Output Port 1 (General purpose output) or RS-485 Direction Control Signal. RS-
485 direction control can be selected when FCTR Bit-3 is set to “1”. During data
transmit cycle, RS485 pin is low. An inverter is usually required before connecting
to RS-485 Transceiver.
39
35
I Reset Input (active high). When it is asserted, the UART configuration registers are
reset to default values, see Table 15.
44
42 Pwr Power supply input. All inputs are 5V tolerant except for XTAL1 for devices with top
mark date code of "F2 YYWW" and newer. Devices with top mark date code of "EC
YYWW" and older do not have 5V tolerant inputs.
22
18 Pwr Power supply common ground.
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
Factory Test Mode
For devices with top mark date code of "EC YYWW" and older devices, please note that if IOR# (or IOR) and
IOW# (or IOW) are both asserted simultaneously, the 850 will enter a Factory Test Mode. The most noticeable
Factory Test Mode symptom is the continuous transmission of the same character on the TX pin. This usually
happens during power-up or when another device in the design requires both signals to be asserted
simultaneously (like an SDRAM). A solution to this would be to OR (AND if using active-high signals) the chip
selects with the read and write signals to the XR16C850 as shown below:
CS#
(from CPU
or PLD)
IOR#
IOW#
CS2#
IOR#
XR16C850
IOW#
(Active Low Signals)
CS
(from CPU
or PLD)
CS0 or CS1
IOR
IOW
IOR
XR16C850
IOW
(Active High Signals)
For devices with top mark date code of "F2 YYWW" and higher devices, the solution for the Factory Test Mode
given in the figure above has been incorporated into the UART. It will only enter Factory Test Mode when all
three signals (chip select, read and write) are asserted simultaneously.
7