XR16C850CM-F Datasheet, PDF (43/56 Pages) Exar Corporation – 2.97V TO 5.5V UART WITH 128-BYTE FIFO

xr
REV. 2.3.1
XR16C850
2.97V TO 5.5V UART WITH 128-BYTE FIFO
AC ELECTRICAL CHARACTERISTICS
TA=0^O TO 70^OC (-40^O TO +85^OC FOR INDUSTRIAL GRADE PACKAGE), VCC IS 2.97V TO 5.5V, 70 PF LOAD WHERE
APPLICABLE
SYMBOL
PARAMETER
CLK Clock Pulse Duration
LIMITS
3.3V
MIN
MAX
LIMITS
5.0V
MIN
MAX
45
30
UNIT
ns
OSC Crystal Frequency (top mark date code "EC YYWW" and older)
8
24 MHz
OSC Crystal Frequency (top mark date code "F2 YYWW" and newer)
16
24 MHz
OSC External Clock Frequency
(top mark date code "EC YYWW" and older)
22
33 MHz
OSC External Clock Frequency
(top mark date code "F2 YYWW" and newer)
22
36 MHz
TAS Address Setup Time (AS# tied to GND)
5
0
ns
TAH Address Hold Time (AS# tied to GND)
(top mark date code of "EC YYWW" and older)
10
5
ns
TAH Address Hold Time (AS# tied to GND)
(top mark date code of "F2 YYWW" and newer)
0
0
ns
TCS Chip Select Width
75
50
ns
TRD IOR# Strobe Width
75
50
ns
TDY Read/Write Cycle Delay
75
50
ns
TRDV Data Access Time
35
25
ns
TDD Data Disable Time
0
25
0
15
ns
TWR IOW# Strobe Width
75
50
ns
TDS1 Data Setup Time (AS# tied to GND)
20
15
ns
TDH1 Data Hold Time (AS# tied to GND)
5
5
ns
T_ASW
T_AS1
T_AH1
T_AS2
T_AH2
T_CS1
T_CSH
T_CS2
T_RD1
Address Strobe Width
Address Setup Time (AS# used)
Address Hold Time (AS# used)
Address Setup Time (AS# used)
Address Hold Time (AS# used)
Delay from Chip Select to AS#
Delay from AS# to Chip Select
Delay from AS# to Chip Select
Delay from AS# to Read
75
50
ns
5
5
ns
10
5
ns
5
5
ns
10
5
ns
5
5
ns
10
5
ns
5
5
ns
10
5
ns
43