XR16C850CM-F Datasheet, PDF (3/56 Pages) Exar Corporation – 2.97V TO 5.5V UART WITH 128-BYTE FIFO

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REV. 2.3.1
ORDERING INFORMATION
PART NUMBER
PACKAGE
XR16C850CJ
XR16C850CM
XR16C850IJ
XR16C850IM
44-Lead PLCC
48-Lead TQFP
44-Lead PLCC
48-Lead TQFP
XR16C850
2.97V TO 5.5V UART WITH 128-BYTE FIFO
OPERATING TEMPERATURE
RANGE
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
DEVICE STATUS
Active
Active
Active
Active
PIN DESCRIPTIONS
NOTE: Pin type: I=Input, O=Output, IO= Input/output, OD=Output Open Drain.
NAME
44-PIN
PLCC
48-PIN
TQFP
TYPE
DESCRIPTION
INTEL BUS MODE INTERFACE. THE SEL PIN IS CONNECTED TO VCC.
A2
29
26
I Address data lines [2:0]. A2:A0 selects internal UART’s configuration registers.
A1
30
27
A0
31
28
D0
2
43 I/O Data bus lines [7:0] (bidirectional).
D1
3
44
D2
4
45
D3
5
46
D4
6
47
D5
7
2
D6
8
3
D7
9
4
IOR#
24
19
I Input/Output Read (active low). The falling edge instigates an internal read cycle
and retrieves the data byte from an internal register pointed by the address lines
[A2:A0], places it on the data bus to allow the host processor to read it on the lead-
ing edge. Either an active IOR# or IOR is required to transfer data from 850 to CPU
during a read operation. If not used, connect this pin to VCC. Caution: SEE”FAC-
TORY TEST MODE” ON PAGE 7.
IOR
25
20
I Input/Output Read (active high). Same as IOR# but active high. Either an active
IOR# or IOR is required to transfer data from 850 to CPU during a read operation.
If not used, connect this pin to GND. During PC Mode, this pin becomes A3. Cau-
tion: SEE”FACTORY TEST MODE” ON PAGE 7.
IOW#
20
16
I Input/Output Write (active low). The falling edge instigates the internal write cycle
and the rising edge transfers the data byte on the data bus to an internal register
pointed by the address lines [A2:A0]. Either an active IOW# or IOW is required to
transfer data from 850 to the Intel type CPU during a write operation. If not used,
connect this pin to VCC. Caution: SEE”FACTORY TEST MODE” ON PAGE 7.
IOW
21
17
I Input/Output Write (active high). The rising edge instigates the internal write cycle
and the falling edge transfers the data byte on the data bus to an internal register
pointed by the address lines [A2:A0]. Either an active IOW# or IOW is required to
transfer data from 850 to the Intel type CPU during a write operation. During PC
Mode, this pin becomes A8. If not used, connect this pin to GND. Caution:
SEE”FACTORY TEST MODE” ON PAGE 7.
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