XR16C850CM-F Datasheet, PDF (56/56 Pages) Exar Corporation – 2.97V TO 5.5V UART WITH 128-BYTE FIFO

XR16C850
2.97V TO 5.5V UART WITH 128-BYTE FIFO
xr
REV. 2.3.1
3.0 UART INTERNAL REGISTERS ...........................................................................................................25
TABLE 7: XR16C850 UART INTERNAL REGISTERS ................................................................................................................. 25
TABLE 8: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1......................................... 26
4.0 INTERNAL REGISTER DESCRIPTIONS .............................................................................................27
4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY ............................................................................... 27
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................ 27
4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE .............................................................................. 27
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................. 27
4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION ................................................................ 28
4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY ............................................................................... 29
4.4.1 INTERRUPT GENERATION: ...................................................................................................................................... 29
4.4.2 INTERRUPT CLEARING: ........................................................................................................................................... 29
TABLE 9: INTERRUPT SOURCE AND PRIORITY LEVEL ....................................................................................................................... 30
4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ...................................................................................... 30
TABLE 10: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION .......................................................................... 32
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE ...................................................................................... 32
TABLE 11: PARITY SELECTION ........................................................................................................................................................ 33
4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE 34
4.8 LINE STATUS REGISTER (LSR) - READ ONLY ........................................................................................... 35
4.9 MODEM STATUS REGISTER (MSR) - READ ONLY .................................................................................... 36
4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE .................................................................................... 36
4.11 ENHANCED MODE SELECT REGISTER (EMSR) ...................................................................................... 37
TABLE 12: SCRATCHPAD SWAP SELECTION .................................................................................................................................... 37
4.12 FIFO LEVEL REGISTER (FLVL) - READ-ONLY .......................................................................................... 37
4.13 BAUD RATE GENERATOR REGISTERS (DLL AND DLM) - READ/WRITE .............................................. 37
4.14 DEVICE IDENTIFICATION REGISTER (DVID) - READ ONLY .................................................................... 37
4.15 DEVICE REVISION REGISTER (DREV) - READ ONLY .............................................................................. 37
4.16 TRIGGER LEVEL / FIFO DATA COUNT REGISTER (TRG) - WRITE-ONLY ............................................. 37
4.17 FIFO DATA COUNT REGISTER (FC) - READ-ONLY .................................................................................. 37
4.18 FEATURE CONTROL REGISTER (FCTR) - READ/WRITE ........................................................................ 38
TABLE 13: TRIGGER TABLE SELECT................................................................................................................................................ 38
4.19 ENHANCED FEATURE REGISTER (EFR) .................................................................................................. 39
TABLE 14: SOFTWARE FLOW CONTROL FUNCTIONS ........................................................................................................................ 39
4.20 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE ................ 40
TABLE 15: UART RESET CONDITIONS ...................................................................................................................................... 41
ABSOLUTE MAXIMUM RATINGS...................................................................................42
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)..................................................42
ELECTRICAL CHARACTERISTICS ................................................................................42
DC ELECTRICAL CHARACTERISTICS ..............................................................................................................42
AC ELECTRICAL CHARACTERISTICS ..............................................................................................................43
TA=0O TO 70OC (-40O TO +85OC FOR INDUSTRIAL GRADE PACKAGE), VCC IS 2.97V TO 5.5V, 70 PF LOAD WHERE
APPLICABLE..................................................................................................................................................43
FIGURE 17. CLOCK TIMING............................................................................................................................................................. 45
FIGURE 18. MODEM INPUT/OUTPUT TIMING .................................................................................................................................... 45
FIGURE 19. DATA BUS READ TIMING IN INTEL BUS MODE WITH AS# TIED TO GND ......................................................................... 46
FIGURE 20. DATA BUS WRITE TIMING IN INTEL BUS MODE WITH AS# TIED TO GND ........................................................................ 46
FIGURE 22. DATA BUS WRITE TIMING IN INTEL BUS MODE USING AS#............................................................................................ 47
FIGURE 21. DATA BUS READ TIMING IN INTEL BUS MODE USING AS# ............................................................................................. 47
FIGURE 24. DATA BUS WRITE TIMING IN PC MODE ........................................................................................................................ 48
FIGURE 23. DATA BUS READ TIMING IN PC MODE.......................................................................................................................... 48
FIGURE 25. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] ............................................................................................ 49
FIGURE 26. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] .......................................................................................... 49
FIGURE 27. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] .......................................................................... 50
FIGURE 28. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] ........................................................................... 50
FIGURE 29. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] .............................................................. 51
FIGURE 30. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] ............................................................... 51
PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 mm)....................................................................................52
PACKAGE DIMENSIONS (44 PIN PLCC) .........................................................................................................53
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